To encourage student participation and recognize excellence in the field of design for testability, the IEEE Computer Society Test Technology Technical Council (TTTC) established the TTTC James Beausang Student Award for DFT.

This Award honors the memory of Dr. James Beausang, a well-known researcher and practitioner in Design for Testability and Test Synthesis. The Award endowment came from private, corporate and IEEE funding.

The TTTC Beausang Award was granted exclusively to undergraduate or graduate student(s) listed as primary authors of a qualifying paper. Only papers accepted at the VLSI Test Symposium or the International Test Conference qualify. The paper content may be derived from university or industrial research and development. Eligible subject areas include test architectures, synthesis and analysis research applied to Scan, Design for Testability, Test Synthesis, BIST, Boundary Scan and Embedded Core Test. The Award was granted four times: VTS 1999, ITC 1999, VTS 2000, and ITC 2000.

Winners of the Award were:

  • VTS-1999: Hyungwon Kim, University of Michigan – Lead author of the paper H. Kim and J. P. Hayes, “Delay Fault Testing of Designs with Embedded IP Cores”
  • ITC-1999: Jayabrata Ghosh-Dastidar, University of Texas at Austin , Lead author of the paper J. Ghosh-Dastidar, D. Das and N. Touba, “Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information”
  • VTS-2000: Anshuman Chandra, Duke University, USA : “Test Data Compression for System-On-A-Chip using Gulomb Codes”
  • ITC-2000: Nicola Nicolici, University of Southampton, England, Lead author of the paper N. Nicolici and B. M. Al-Hashimi “Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths”

The Award benefits to the author(s) are:

  1. Recognition of the outstanding student achievement at the Plenary Session of the conference in the same year and in the TTTC Newsletter and other IEEE Publications
  2. A $500 check
  3. A Plaque or Certificate of Recognition
  4. Complementary registration in the following year at a TTTC Workshops: ITSW, ETW or TECS (other TTTC workshop access may also be arranged)
  5. Publication of a revised and extended version of the paper is made in IEEE Design & Test Magazine

For further information, please contact: Ken WAGNER

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022