Technical Activity Committee on FPGA TESTING

TAC Chair:  Michel RENOVELL, renovell@lirmm.fr

This FPGA Testing TAC has been recently formed in November 1999 with the aim of stimulating research and discussions around the new topic of FPGA testing.

Programmable logic in the form of field-programmable gate arrays has become now a widely accepted design approach for low- and medium-volume computing applications.

Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology.

Only recently researchers have addressed the problem of testing this kind of circuits. The goal of the TAC is to provide an informal forum, bringing together designers and test researchers to address the problem of FPGA testing.

Upcoming conferences and symposia

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2024

Submission of title, abstract, and author list: 23 February, 2024
Final Paper Submission: 29 February, 2024
Author Notification: 09 April, 2024
Conference Dates: July 3 – 5, 2024

IEEE European Test Symposium (ETS) 2024
Paper registration: December 8, 2023
Paper PDF upload: December 16, 2023
Notification: February 16, 2024
Conference: May 20-24, 2024

IEEE VLSI Test Symposium (VTS) 2024
Paper registration: October 9, 2023
Paper PDF upload: October 15, 2023
Questions to authors: December 9, 2023
Submission of rebuttal: December 14, 2023
Notification: December 23, 2023
Camera-ready upload: February 03, 2024
Conference: April 22-24, 2024