Technical Activity Committee on FPGA TESTING

TAC Chair:  Michel RENOVELL, renovell@lirmm.fr

This FPGA Testing TAC has been recently formed in November 1999 with the aim of stimulating research and discussions around the new topic of FPGA testing.

Programmable logic in the form of field-programmable gate arrays has become now a widely accepted design approach for low- and medium-volume computing applications.

Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology.

Only recently researchers have addressed the problem of testing this kind of circuits. The goal of the TAC is to provide an informal forum, bringing together designers and test researchers to address the problem of FPGA testing.

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022