Hardware Security and Trust

Technical Activity Committee on HARDWARE SECURITY AND TRUST

TAC Chair: Jim PLUSQUELLIC, jimp@ece.unm.edu
TAC Vice-Chairs: Mohammad TEHRANIPOOR, tehrani@engr.uconn.edu
Giorgio DI NATALE, giorgio.dinatale@lirmm.fr


A wide range of applications, from secure RFID tagging to high-end trusted computing, relies on dedicated and trusted hardware platforms. The security and trustworthiness of such hardware designs are critical to their successful deployment and operation. Recent advances in tampering and reverse engineering show that important challenges lie ahead. For example, secure electronic designs may be affected by malicious circuits, Trojans that alter system operation. Furthermore, dedicated secure hardware implementations are susceptible to novel forms of attack that exploit side-channel leakage, faults, or test infrastructures. Third, the globalized, horizontal semiconductor business model raises concerns of trust and intellectual-property protection.


  • Trojan Detection and Isolation
  • Side channel Attacks and Countermeasures
  • Fault-based Attacks and Countermeasures
  • Intellectual Property Protection and Metering
  • Tools and Methodologies for Secure Hardware Design
  • Hardware Architectures for Cryptography
  • Hardware Security Primitives: PUFs and TRNGs
  • Trusted Platform and System Level Hardware Security
  • Interaction of Secure Hardware and Software
  • Non-destructive Reverse Engineering
  • CAD Tool Security and Trust
  • Supply Chain Security
  • Test and Security

 Related Events

  • HOST: IEEE International Symposium on HARDWARE-ORIENTED SECURITY and TRUST
  • IOLTS (Topics: Secure circuit design, Fault-based attacks and counter measures)
  • DATE: Conference on Design, Automation and Test in Europe
  • VTS’2011 (Session 4b: Security)
  • VTS’2010 (Special Session 11B: Hot Topic: Hardware Security: Design, Test and Verification Issues)
  • VTS’2009 (Session 11B: Emergent Technology and Security
  • Tutorials on Test and Security (LATW’09, ETS’09, DDECS’10)

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022