Technical Activity Committee on SiP and 3D IC Testing

TAC Chair:

Yervant ZORIAN, y.zorian@computer.org

All aspects of SiP and 3D IC testing including but not limited to:

• wafer level, die level and stack level testing; known-good die technology;
• Through Silicon Via fault models and tests;
• temporary pressure- based and fixed contact-based carrier test;
• known-good die testability approaches;
• mechanical and contactless substrate testing;
• SiP and 3D IC yield models;
• ATE for SiP testing;
• assembled module level test, testability, diagnosis and repair;
• SiP and 3D IC level BIST;
• testing printed circuit boards with SiPs and/or 3D ICs.