High Level D&T

Technical Activity Committee on HIGH-LEVEL DESIGN AND TEST

This high-level design and test TAC was formed in 1995 with the aim of stimulating research and discussions on test and validation methodologies for ICs and systems specified using high level descriptions, where high-level refers to register-transfer, behavioral, and system level specifications.

The TAC has held annual workshops (IEEE High-Level Design Validation and Test 1996-2002) on the topic. The TAC has also been active in organizing technical sessions at various TTTC sponsored meetings.

The goal of the TAC, and the HLDVT workshops, is to provide an informal forum, bringing together designers and test and validation researchers working in validating, debugging, and testing designs in an effort to address high-level design validation and test issues concurrently.

While the TAC itself has not been particularly active in recent years, the HLDVT workshop continues to thrive. For those interested in pursuing this subject, there are several very active areas to pursue, including the SystemC project and the open-source TestBuilder project (which is sponsored by Cadence Design Systems).

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022