To encourage female participation and recognize excellence in the field of test technology, TTTC sponsors the TTTC Naveena Nagi Award Program in 2001 and 2002. The Award honors the memory of Dr. Naveena Nagi, a well-known researcher and practitioner in Analog and Mixed-Signal Test domain.

The award will be granted four times at the VLSI Test Symposium (VTS 2001, VTS 2002, VTS 2003, VTS 2004).

This Memorial Award has been endowed by with individual, corporate and organizational donations to the Naveena Nagi Memorial Fund. The award will be granted to females listed as primary authors of accepted papers.

For further information, please contact: Yervant ZORIAN

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022