Verification and Test

Technical Activity Committee on VERIFICATION AND TEST

TAC Co-Chair:  Magdy S. ABADIR,

Sujit Dey,

As designs get larger every year, the two major problems faced by the semiconductor industry are to ensure that there are no bugs in the design and that the manufactured chips are defect-free. Given the rate of advance of the size, complexity and performance capabilities of integrated circuits, new directions need to be explored to solve problems in verification and test.

Although research in test and verification is exploring new directions which can deal with the complexities of emerging designs, the research communities in these areas have interacted very little. New techniques developed for verification are not applied to test, and sometimes long understood test strategies are not considered for formal verification. The goal of this TAC is to bring together the verification and test communities.

Simulation is the primary means used to validate the correctness of a design today. This should be the first area where the issues in verification and test are considered at the same time. Ultimately, formal verification techniques should be examined by the test community. (Test generation algorithms are beginning to be used to support formal verification).

We hope that this interaction will spur the development of tools for test generation and for formal verification that employ methods that are common to both domains.

One area of activity which will benefit both communities is the development of complex, public-domain benchmark designs. These will serve as a vehicle to spur the development of new techniques which can deal effectively with complexity, and will also serve to compare different techniques for solving various problems in the test and verification areas.

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022