Silicon Debug and Diagnosis

Technical Activity Committee on Silicon Debug and Diagnosis


The scope of the Silicon Debug and Diagnosis (SDD) TAC considers all aspects of prototype bring-up and debug, from systems to silicon. It includes, but is not limited to:

  • Structured debug architectures;
  • Techniques and methodologies;
  • Debug requirements and partitioning;
  • Implementation and synthesis of dedicated Design for Debug (DFD) features;
  • Reuse of existing DFT features (e.g., scan, BIST, etc.) for debug;
  • Design tradeoffs and economics of DFD;
  • Debug and diagnosis tools.

Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration with shortened development cycles. Moreover, with the advent of System on Chip (SoC) design methodologies and nanometer design tools, new levels of productivity gains are taking place, and ICs will continue to grow in complexity. Undoubtedly, these advances on the design side are placing immense pressure on design verification efforts.

While there have been many improvements in verification tools and methodologies, such as with simulation tools, formal verification, timing analysis tools, physical design tools and prototype emulation, these are far from optimum solutions for today’s most complex designs. What’s more, as design complexity continues to increase there is a growing class of design problems, and design marginalities, that will inevitably escape pre-silicon verification, and can only be discovered during prototype bring up. Additionally, verification is currently reported to be over 50% of the design effort and resources, with system verification being the largest effort by far. Consequently, design verification and analysis are becoming a major bottleneck for timely design of complex systems and SoCs. We are at a point in time where guaranteeing that first silicon will work perfectly in a prototype system is either an impractical task, or is simply not possible.

It is very likely that we have reached a state where systems can not be fully and efficiently verified until a hardware prototype exists in the lab.

Discovering and isolating design errors during the prototype debug phase of the design cycle can be very costly, due to debug time and effort, and the associated design re-spins. It also has a highly visible impact on product time-to-market. Extending the debug phase slows the time-to-volume of new products considerably, in an environment where rapidly changing technology is shrinking development cycles and time-to-profit is a critical factor in remaining competitive. It follows then that speeding up debug and shortening the hardware prototype verification cycle will reduce costs and hasten time-to-market. Improving debug productivity can therefore have a high return on investment. If designers can spend less time debugging, with improved productivity, new products will get to market faster and they will be able to start designing the next generation of products sooner. Unfortunately, with increased circuit complexity and advanced system packaging debug is becoming more difficult. Physical access for debug is often difficult, or impossible, making traditional debug methods unusable. As a result, new methods and tools will be needed in order to provide for silicon debug and diagnosis of the next generation of silicon and systems.

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022