Economics of Test

Technical Activity Committee on Economics of Test

TAC Co-Chair: 

Magdy S. ABADIR,

Anthony P. AMBLER,

This technical area has been active with TTTC help since 1991 and has held several workshops devoted to the topic of the Economics of Design, Manufacturing and Test.

Test Economics covers a very difficult, emotive and yet crucial area of design choice. Questions such as:

  • Do I use DFT?
  • What DFT do I use?
  • What is it’s benefit?
  • Doesn’t test always cost too much?
  • . . . and many more, are hopefully addressed through technical meetings and publications organized by this TAC.

Economics is the one factor that is common in any design, manufacturing and test process, and enables a much more rational approach to decisions in these areas. There are still uncertainties that must be considered, such as time-to-market impact that are, perhaps more difficult to accurately parameterize, but nevertheless economics analysis can be a very useful tool in the design and production process.

One very prominent example of an issue directly addressed by test economics is that area overhead in chip-level testability design directly equates to increased cost, therefore, any such method is rejected. Although the perception of costs of area overhead has greatly reduced, there is still a large amount of skepticism.

One of ITC’s Keynote Speakers in 1992 introduced the term “QUIF – Quality Improvement Factor” for quantifying the benefits of DFT – he asked that the term ‘area overhead’ be banned.

An obvious ways of measuring QUIF is to use economics.

This TAC provides a mechanism for issues concerning the economic evaluation of technology choices to aired and discussed – many case study examples from industry have been presented, and academics are encouraged to participate so that test education can be better served.


  •  Economics of Design and Test for Electronic Circuits and Systems, Proceedings of the 1st Intl. Workshop on Test Economics, Ambler, Abadir & Sastry (eds.), Ellis Horwood, 1992, ISBN 0-13-224767-4.
  • Economics of Electronic Design, Manufacture and Test, Proc. of the 2nd Int. Workshop on Test Economics, Abadir & Ambler (eds.), Luwer, 1994, ISBN 0-7923-9471-2.
  • Economics of Design, Test, and Manufacturing, Proc. of the 3rd Intl. Workshop on Test Economics, IEEE Computer Society Press, ISBN 0-8186-6595-5.
  • IEEE Design & Test Journal, special issue on Test Economics, September 1997.


  1. Test Economics and Design for Testability for Electronic Circuits and Systems, Dislis, Dick, Dear & Ambler, published by Ellis-Horwood (Prentice Hall), 1994.

Conferences and symposia

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023

Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

IEEE VLSI Test Symposium 2023
Title+Abstract: November 5, 2022
Paper: November 11, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

IOLTS 2022
Paper submission: May 10, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022