Defect Tolerance

Technical Activity Committee on DEFECT TOLERANCE

TAC Chair: Vincenzo PIURI,
TAC Vice-Chairs: Cecilia METRA,
Nohpill PARK,

Defect Tolerance deals with a broad range of highly specialized topics in several theoretical, practical, and application areas of defect and fault tolerance in VLSI devices and systems. Main problems addressed by the committee include:

    Analysis of defect distributions and prediction in VLSI devices and systems,
  • Yield analysis and prediction,
  • Yield enhancement, production planning and production process management,
  • Design techniques and methodologies for yield enhancement of VLSI/WSI devices and systems,
  • Design techniques and methodologies to embed testing strategies and supports in the VLSI IC for defect detection and localization,
  • Configurable VLSI architectures to support defect confinement and enhance the yield,
  • Life-time detection and correction techniques, methodologies and supports to detect the presence of errors due to faults and correct them in VLSI devices and systems,
  • Design of self-checking VLSI/WSI architectures,
  • Reconfigurable VLSI/WSI architectures to confine life-time faults,
  • Fault tolerant VLSI/WSI systems,
  • CAD for fault-tolerant VLSI/WSI design and analysis,
  • High-level synthesis and co-design techniques for fault tolerant VLSI architectures,

…and many more.

This TAC is highly committed to present and disseminate the most relevant results of academic and industrial research and practice in the above areas.

In particular, the Defect Tolerance TAC organizes the annual International Symposium on Defect and Fault Tolerance in VLSI Systems, special sessions in other workshops and conferences, special issues in international journals, tutorials, and cooperate in organizing the International On-line Testing Workshop.


  •  IEEE Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems, S. Francisco, CA, USA, 2001
  • IEEE Proceedings of the Instrumentation and Measurement Technology Conference, Budapest, Hungary, 2001 (special session on VLSI)
  • Proceedings of the Euromicro Conference on Massively Parallel Computing Systems, Ischia, Italy, 2002 (special session on Test)
  • Special Issue on Function Integrated Information Systems, IEICE Transactions on Information and Systems, 2001
  • IEEE Proceedings of the Instrumentation and Measurement Technology Conference, Anchorage, AK, USA, 2002 (special session on “Recent trends in test synthesis in VLSI”, “Hybrid and fault-tolerant sensor systems”, “Resilient computing for instrumentation and distributed sensors in harsh environments”)
  • Special Issue on Defect and Fault Tolerance in VLSI Systems, Journal of System Architectures, Elsevier Publisher, 2002


Upcoming conferences and symposia

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2024

Submission of title, abstract, and author list: 23 February, 2024
Final Paper Submission: 29 February, 2024
Author Notification: 09 April, 2024
Conference Dates: July 3 – 5, 2024

IEEE European Test Symposium (ETS) 2024
Paper registration: December 8, 2023
Paper PDF upload: December 16, 2023
Notification: February 16, 2024
Conference: May 20-24, 2024

IEEE VLSI Test Symposium (VTS) 2024
Paper registration: October 9, 2023
Paper PDF upload: October 15, 2023
Questions to authors: December 9, 2023
Submission of rebuttal: December 14, 2023
Notification: December 23, 2023
Camera-ready upload: February 03, 2024
Conference: April 22-24, 2024