Test Synthesis

Technical Activity Committee on TEST SYNTHESIS

TAC Chair:  Scott DAVIDSON, scott.davidson@eng.sun.com

Test synthesis, loosely defined as “the automated synthesis of hardware testability structures during the process of design, working from high-level description languages,” is attracting more and more practitioners and researchers of DFT as it has been viewed as the “enabling technology of Design-for-Test.”

There is considerable interest in the integration of design and test activities and automatic synthesis of DFT hardware has become necessary in many design environments. However, true integration, seamless and invisible, is not yet reality but the signs are that engineers are beginning to appreciate the need and eager to understand methodology. Also, robust gate-level tools are now available and the user base is increasing. On the other hand, researchers and tool developers are focusing on new techniques and tools working at RTL and behavioral levels.

In addition, test synthesis is beginning to cover more than the traditional stuck-at faults. Work is being done on test structures for delay faults, crosstalk faults, and faults in high-speed I/O. Test synthesis is seen as crucial in holding down the cost of test by enabling the use of lower cost ATE, and in supporting board and system level test by leveraging test structures inserted in ICs.

This technical area has been active with TTTC help since 1993 and has held 9 workshops devoted to the topic of Test Synthesis (1994-2002), one special Test Synthesis seminar at ITC’94 [1] with 13 presentations and a couple of special issues in magazines and journals [2] [3] [6].

This TAC has formed a benchmark subcommittee which has collected a set of realistic benchmark circuits for distribution to researchers and tool developers to drive DFT and test synthesis technology. A special issue of IEEE Design & Test of Computers magazine has been published on benchmarking. [6]


    1. Digest of Papers, “Test Synthesis Seminar,” IEEE International Test Conference, 1994.
    2. IEEE Design & Test of Computers magazine, “Test Synthesis” Special Issue, ed. Ben Bennetts, Summer 1995.
    3. Journal of Electronic Testing, Theory and Practice (JETTA), Special Issue on Test Synthesis, ed. Tim Cheng, K.K. Saluja & H.-J Wunderlich, Aug. 1997.
    4. “Synthesis for Testability,” IEEE Design & Test of Computers magazine Roundtable, December 1990.
    5. “Test Synthesis,” IEEE Design & Test of Computers magazine Roundtable, Spring 1994.
    6. IEEE Design & Test of Computers magazine, “Benchmarking” Special Issue, eds. Scott Davidson and Justin Harlow, July-September 2000.

Upcoming conferences and symposia

IEEE VLSI Test Symposium 2024
Paper registration: October 9, 2023
Paper PDF upload: October 15, 2023
Questions to authors: December 9, 2023
Submission of rebuttal: December 14, 2023
Notification: December 23, 2023
Camera-ready upload: February 03, 2024

ITC 2023
Paper title/abstract due: March 20, 2023 extended to April 3, 2023
Paper final PDF due: April 3, 2023 extended to April 17, 2023
Author notification: June 12, 2023 delayed until June 23, 2023
Final manuscript due: July 17, 2023
Authors are also invited to submit a single-page poster prop

IOLTS 2023
Title and Abstract registration: March 23, 2023
Paper submission: March 27, 2023
Notification of acceptance: May 10, 2023
Camera Ready: June 07, 2023

19th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2023
Paper registration: December 23, 2022
Paper submission: January 9, 2023

IEEE European Test Symposium 2023
Title+Abstract: December 9, 2022
Paper: December 16, 2022

DATE 2023
Title+abstract: September 18, 2022 (AoE)
Paper: September 25, 2022 (AoE)

IEEE Asian Test Symposium 2022
Abstract & Full Paper Submission Deadline: July 1st, 2022 (AoE)

ITC India 2022
Abstract & Full Paper Submission Deadline: May 9th, 2022

LATS 2022
Title+abstract: May 6, 2022
Paper: May 13, 2022