TTTC’s E. J. McCluskey Doctoral Thesis Award

The Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. The Award is given to the winner of a two-stage contest with semi-finals held at TTTC-sponsored conferences, symposia or workshops. The winners of the semi-finals, determined by jurys composed of industrial experts, will compete against each other in the finals, held at a major TTTC-sponsored conference or symposium. This major Award is named after Prof. Edward J. McCluskey, a key educator and mentor in the fields of test technology, logic design, and reliability.

Call for Participation 2019

We are happy to announce that in 2019, the Contest will be coming held in 4 locations: the  Asian Test Symposium, the European Test Symposium, the Latin-America Test Symposium and the  VLSI Test Symposium


Because of ATS being held after or really close to ITC, the Asian semi-final for the TTTC’s E. J. McCluskey Doctoral Thesis Award is usually held the year before.


All active doctoral students working on test-related topics and recent graduates who graduated 2018 or later are eligible for the Award. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results. Prospective contestants submit a summary of their thesis work (up to 2000 words), possibly accompanied by one additional page of figures and references. They are free to submit up to three published referenced as supporting material, which are considered by the jury on an optional basis. The abstract should clearly address the following:

  • define the problem and its relevance to industry,
  • describe existing industrial practices for solving the problem, and
  • explain the proposed methodology (and any pertinent case study) and how it advances the theory and/or practice in the particular field.
  • A student can freely choose the regional (semi-finals) site to submit the summary. Submissions to multiple regional sites are prohibited.


The 4 semi-finals sites for the Best Doctoral Thesis Award 2019:

  1. VLSI Test Symposium 2019 (VTS’19), local coordinator Karimi Naghmeh
  2. European Test Symposium 2019 (ETS’19), local coordinator Said Hamdioui
  3. Latin Americ Test Symposium 2019 (LATS’19), local coordinator José Lipovetzky
  4. Asian Test Symposium 2018 (ATS’18), local coordinator Hiroshi Takahashi

For submission information, please refer to the Local Coordinator at the conference website.

For general inquiries, direct your questions to the Global Coordinator,  Michele Portolan (Grenoble-INP, France).


Based on the submitted abstracts, a set of semi-finalists will be selected for the semi-finals of the contest. Semi-finals could be canceled if the numbers of submissions is inadequately low, in which case candidates will be invited to take part in another semi-final. This round includes a short (seven-minute) slot for oral presentation during a dedicated session at the semi-final event. The jury will judge the presentations, and the winner of the semi-final will be announced during the event.

The finalists will present their work in a 30-minute presentation at ITC’19, and the winner will be determined by a panel of academic and industrial experts. The Award is given to the winning student and the advisor of the thesis.


Past recipients


Name Year Result Thesis Title Location
Francisco Elias Rangel-Patiño,   ITESO – The Jesuit University of Guadalajara, Mexico 2018 1st place Winner Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation LATS 18
Justyna Zawada, Poznan University of Technology 2018 Runner Up On new class of test points and their applications ETS 18
Muhammad Yasin, New York University, United States and UAE 2018 Runner Up Towards Provably Secure Logic Locking for Hardening Hardware Security VTS 18
Fakir Sharif Hossain, Nara Institute of Science and Technology, (NAIST), Japan 2018 Runner Up Variation-Aware Hardware Trojan Detection through Power Side-channe ATS 17
Yuming Zhuang, Iowa State University 2017 1st Place Winner Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements VTS 2017
Surajit Kumar Roy, Indian Institute of Engineering Science and Technology 2017 Runner Up Design-for-test and test optimisation for 3D SOCs ATS 2016
Boyang Du, Politecnico di Torino, Italy 2017 Runner Up Fault Tolerant Electronic System Design ETS 2017
Ran Wang, Duke University 2016 1st Place Winner Testing of Interposer-Based 2.5D Integrated Circuits VTS 2016
Panagiota Papavramidou, TIMA, Grenoble 2016 Runner Up Memory repair architectures for high defect densities ETS 2016
Lien Wei-Cheng, National Cheng Kung University, Taiwan 2016 Runner Up Output bit selection methodology for test response compaction ATS 2015
Eduardo Chielle, Federal University of Rio Grande Do Sul (UFGRS) 2016 Runner Up Selective Software-Implemented Hardware Fault Tolerance Techniques to Detect Soft Errors in Processors with Reduced Overhead LATS 2016
Fabian Oboril, KIT Karlsruhe 2015 1st Place Winner Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocess ITC 2015
Sergej Deutsch, Duke University 2015 Runner Up Test and Debug Solutions for 3D-Stacked Integrated Circuits ITC 2015
Li Jiang , The Chinese University of Hong Kong, Hong Kong 2015 Runner Up. Yield and reliability enhancement for 3D ICs ITC 2015
Samah Saeed, 2014 1st Place Winner DfT Approaches and Security Challenges in the Scan Design ITC 2014
NYU Polytechnic
School of Engineering
Julio César Vázquez Hernández, 2014 Runner Up Aging Robust Monitoring and Techniques to Improve Performance on Digital Systems ITC 2014
National Institute for Astrophysics
Optics and Electronics (INAOE)
Luca Cassano, 2014 Runner Up Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs ITC 2014
University of Pisa
Louay Abdallah, 2013 1st Place Winner Non-intrusive embedded sensors for RF circuit test ITC 2013
Université Grenoble Alpes
Ke Huang, 2013 2nd Place Winner Fault Modelling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits ITC 2013
Université Grenoble Alpes
Suraj Sindia, 2013 3rd Place Winner High sensitivity test signature for unconventional analog circuit test paradigms ITC 2013
Auburn University
Wing Chiu Tam, 2011 1st Place Winner Physically-Aware Analysis of Systematic Defects in Integrated Circuits ITC 2011
Carnegie Mellon University
Guihai Yan, 2011 2nd Place Winner Online Timing Variation Detection and Tolerance for Digital Integrated Circuits ITC 2011
ICT Beijing
Urban Ingelsson, 2011 3rd Place Winner Investigation into Voltage and Process Variation-Aware Manufacturing Test ITC 2011
University of Southampton, UK
Stephan Eggersgluess, 2010 1st Place Winner Robust Algorithms for High Quality Test Pattern Generation using Boolean Satisfiability ITC 2010
University of Bremen
Hsiu-Ming (Sherman) Chang, 2010 2nd Place Winner Low-Cost Quality Assurance Techniques for High-Performance Mixed-Signal/RF Circuits and Systems ITC 2010
University of California,
Santa Barbara
Alex Roschildt Pinto, 2010 3rd Place Winner Autonomic Methods for Enhancing Communication Quality of Service in Dense Wireless Sensor Networks with Real Time Requirements ITC 2010
Universidade Federal de
Santa Catarina, Brazil
Mahmut Yilmaz, 2009 1st Place Winner Automated Test Grading And Pattern Selection for Small-Delay Defects VTS 2009
Duke University
Erkan Acar, 2009 2nd Place Winner. Architectural and Defect-Based Test and Diagnosis Techniques for RF Integrated Circuits VTS 2009
Duke University
Bo Yang, 2009 3rd Place Winner Design-for-Test Techniques for Securing Scan-based Designs VTS 2009
Polytechnic Institute of NYU
Devanathan Varadarajan, 2008 First Place Winner On Power-safe Testing of System-on-Chips VTS 2008
Indian Institute of Technology,
Madras, India
Sudarshan Bahukudumbi, 2008 Second Place Wafer-Level Testing and Test Planning for Integrated Circuits VTS 2008
Duke University, USA
Francois-Fabien Ferhani, 2008 Third Place Winner Comparing Partial and Complete Test Sets and Test Metrics VTS 2008
Stanford University, USA
Nisar Ahmed, 2007 First Place Winner. High Quality Delay Tests for Very Deep Submicron Designs VTS 2007
University of Connecticut, USA
Nicola Bombieri, 2007 Second Place Winner. A TLM Design for Verification Methodology VTS 2007
University of Verona, Italy
Ahcene Bounceur, 2007 Third Place Winner. CAT Platform for Mixed-Signal Circuit Testing VTS 2007
TIMA Laboratory,
Grenoble, France
Federico di Palma, 2006 First Place Winner. End-of-line Algorithms for Process Diagnosis in Semiconductor Manufacturing VTS 2006
University of Pavia, Italy
Achraf Dhayni, 2006 Second Place Winner. Pseudorandom Built-In Self-Test for MEMS VTS 2006
TIMA Laboratory,
Grenoble, France
Paolo Bernardi, 2006 Third Place Winner Test Techniques for Systems on a Chip VTS 2006
Politecnico di Torino, Italy
Alberto Valdes-Garcia 2005 First Place Winner Development and Implementation of Built-In Testing Techniques for Analog and RF Integrated Circuits VTS 2005
Anand Gopalan 2005 Second Place Winner. Built-In-Self-Test of RF Front-end Circuitry VTS 2005
Haralampos Stratigopoulos 2005 Third place co-winner. Neural Classification of Analog Circuits VTS 2005
Swarup Bhunia 2005 Third place co-winner. Novel Low-Overhead Design-For-Testability Techniques for Improving Testability in Nano-Scaled Circuits VTS 2005