TTTC’s E. J. McCluskey Best Doctoral Thesis Award

The Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. The Award is given to the winner of a two-stage contest with semi-finals held at TTTC-sponsored conferences, symposia or workshops. The winners of the semi-finals, determined by jurys composed of industrial experts, will compete against each other in the finals, held at a major TTTC-sponsored conference or symposium. This major Award is named after Prof. Edward J. McCluskey, a key educator and mentor in the fields of test technology, logic design, and reliability.

Call for Participation 2024

We are happy to announce that in 2024, the Contest will be coming held in 4 locations: the  Asian Test Symposium, the European Test Symposium, the Latin-America Test Symposium and the  VLSI Test Symposium

Because of ATS is held after or really close to ITC, the Asian a semi-final for the TTTC’s E. J. McCluskey Doctoral Thesis Award will be held in 2023

All active doctoral students working on test-related topics and recent graduates who graduated in 2021 or later are eligible for the Award. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results.

Prospective contestants submit a summary of their thesis work (up to 2000 words), possibly accompanied by one additional page of figures and references. They are free to submit up to three published referenced as supporting material, which are considered by the jury on an optional basis. The abstract should clearly address the following:

  • define the problem and its relevance to industry,
  • describe existing industrial practices for solving the problem, and
  • explain the proposed methodology (and any pertinent case study) and how it advances the theory and/or practice in the particular field.
  • A student can freely choose the regional (semi-finals) site to submit the summary. Submissions to multiple regional sites are prohibited.

The 4 semi-finals sites for the Best Doctoral Thesis Award 2024:

  1. VLSI Test Symposium 2024, (VTS’24) local coordinator Ujjwal Guin
  2. European Test Symposium 2024 (ETS’24), local coordinators Alessandro Savino, Alberto Bosio
  3. Latin American Test Symposium 2024(LATS’24), local coordinator TD
  4. Asian Test Symposium 2023 (ATS’23), local coordinator Hiroshi Takahashi
  5.  

For general inquiries, direct your questions to the Global Coordinator, Michele Portolan (Grenoble-INP, France).

Based on the submitted abstracts, a set of semi-finalists will be selected for the semi-finals of the contest. Semi-finals could be canceled if the numbers of submissions is inadequately low, in which case candidates will be invited to take part in another semi-final. Each Semi-Final has its own local rules: please refer to the Local Coordinator for detailed submission instructions. This round usually includes a short (seven-minute) slot for oral presentation during a dedicated session at the semi-final event. The jury will judge the presentations, and the winner of the semi-final will be announced during the event.

The finalists will be invited to submit a summary of their thesis to be included in the ITC’23 Proceedings, and present their work in a dedicated Session. The winner will be determined by a panel of academic and industrial experts. The Award is given to the winning student and the advisor of the thesis.

NAMEAFFILIATIONYEARRESULTTHESIS TITLE
Fernando Fernandes Dos SantosFederal University of Rio Grande do Sul,  Brazil20231st Place WinnerUnderstanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
Anuj DubeyNorth Carolina State University2023Runner-UpA Full-Stack Approach for Side-Channel Secure ML Hardware
Yu LiThe Chinese University of Hong Kong2023Runner-UpTowards Robust Deep Neural Network against Design-time Bugs and Run-time Errors
Prabuddha ChakrabortyUniversity of Florida20221st Place WinnerAI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Sebastian HuhnUniversität Bremen2022Runner-UpNext Generation Design For Testability, Debug and Reliability Using Formal Techniques
Supriyo SrimaniSchool of VLSI Technoogy, IIEST, Shibpur2022Runner-UpTesting of Analog Circuits using Statistical and Machine Learning Techniques
Lizhou WuDelft University of Technology, Netherlands2021WinnerTesting STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
Mengyun LiuDuke University, USA2021FinalistAdaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
Foisal AhmedNara Institute of Science and Technology (NAIST), Japan2021FinalistStudy on High-Accuracy and Low-Cost Recycled FPGA Detection
Mohammad Nasim Imtiaz KhanThe Pennsylvania State University, USA2020WinnerAssuring Security and Reliability of Emerging Non-Volatile Memories
Sarah AzimiPolitecnico di Torino, Italy2020FinalistDigital Design Techniques for Dependable High Performance Computing
Rajit KarmakarDepartment of E&ECE, Indian Institute of Technology Kharagpur, India2020FinalistHardware IP Protection Using Logic Encryption and Watermarking
Rafael B. SchvittzFederal University of Pelotas – UFPEL, Brazil2020FinalistMethods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients
Tao ChenIowa State University, USA2019WinnerThesis title: Built-in Self-Test and Self-Calibration for Analog and Mixed Signal Circuits
Innocent OkwudiliDelft University of Technology, Netherlands2019FinalistReliability Modeling and Mitigation for Embedded Memories
Francisco E. Rangel-PatiñoThe Jesuit University of Guadalajara,  Mexico2018WinnerTransmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Muhammad YasinNew York University Tandon School of Engineering2018FinalistTowards Provably Secure Logic Locking for Hardening Hardware Security
Justyna ZawadaPoznań University of Technology, Poland2018FinalistOn New Class of Test Points and Their Applications
Fakir Sharif HossainGraduate School of Information Science Department of Computer Science and Engineering Nara Institute of Science and Technology, Japan2018FinalistVariation-Aware Hardware Trojan Detection through Power Side-channel
Yuming ZhuangIowa State University2017WinnerAccurate and Robust Spectral Testing with Relaxed Instrumentation Requirements
Surajit Kumar RoyIndian Institute of Engineering Science and Technology2017FinalistDesign-for-Test and Test Optimisation for 3D SOCs
Boyang DuPolitecnico di Torino2017FinalistFault-tolerant Electronic System Design
Ran WangDuke University2016WinnerTesting of Interposer-Based 2.5D Integrated Circuits
Eduardo ChielleFederal University of Rio Grande Do Sul (UFGRS)2016FinalistSelective Software-Implemented Hardware Fault Tolerance Techniques to Detect Soft Errors in Processors with Reduced Overhead​
Panagiota PapavramidouUniversité Grenoble Alpes, TIMA Lab2016FinalistMemory repair architectures for high defect densities
Lien Wei-ChengDept. of Electrical Engr., National Cheng Kung University, Taiwan2016FinalistOutput bit selection methodology for test response compaction
Fabian OborilKIT Karlsruhe2015WinnerCross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocess
Sergej DeutschDuke University2015FinalistTest and Debug Solutions for 3D-Stacked Integrated Circuits
Li JiangThe Chinese University of Hong Kong2015FinalistYield and reliability enhancement for 3D ICs
Samah SaeedNYU  Polytechnic School of Engineering2014WinnerDfT Approaches and Security Challenges in the Scan Design
Luca CassanoUniversity of Pisa, Italy2014FinalistAnalysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
Julio César Vázquez HernándezNational Institute for Astrophysics Optics and Electronics (INAOE), Mexico2014FinalistAging Robust Monitoring and Techniques to Improve Performance on Digital Systems
Louay AbdallahUniversité Grenoble Alpes, TIMA Lab2013WinnerNon-intrusive embedded sensors for RF circuit test
Suraj SindiaAuburn University, Alabama, AL, USA2013FinalistHigh sensitivity test signature for unconventional analog circuit test paradigms
Ke HuangUniversité Grenoble Alpes, TIMA Lab2013FinalistFault Modelling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits
Nathan KuppYale University2012WinnerIntegrated Optimization of Semiconductor Manufacturing: A Machine Learning Approach
Darius SzyszTU Poznan2012FinalistLow power test application with selective compaction in VLSI designs
Wing-Chiu TamCarnegie Mellon University, USA2011WinnerPhysically-Aware Analysis of Systematic Defects in Integrated Circuits
Urban IngelssonUniversity of Southampton, UK2011FinalistInvestigations into Voltage and Process Variation-Aware Manufacturing Test
Guihai YanICT Bejing2011FinalistOnline Timing Variation Tolerance for Digital Integrated Circuits

Upcoming conferences and symposia

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2024

Submission of title, abstract, and author list: 23 February, 2024
Final Paper Submission: 29 February, 2024
Author Notification: 09 April, 2024
Conference Dates: July 3 – 5, 2024

IEEE European Test Symposium (ETS) 2024
Paper registration: December 8, 2023
Paper PDF upload: December 16, 2023
Notification: February 16, 2024
Conference: May 20-24, 2024

IEEE VLSI Test Symposium (VTS) 2024
Paper registration: October 9, 2023
Paper PDF upload: October 15, 2023
Questions to authors: December 9, 2023
Submission of rebuttal: December 14, 2023
Notification: December 23, 2023
Camera-ready upload: February 03, 2024
Conference: April 22-24, 2024