TTTC’s E. J. McCluskey Doctoral Thesis Award

The Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. The Award is given to the winner of a two-stage contest with semi-finals held at TTTC-sponsored conferences, symposia or workshops. The winners of the semi-finals, determined by jurys composed of industrial experts, will compete against each other in the finals, held at a major TTTC-sponsored conference or symposium. This major Award is named after Prof. Edward J. McCluskey, a key educator and mentor in the fields of test technology, logic design, and reliability.

 Call for Participation 2015

We are happy to announce that in 2015, the Contest will be coming held in 4 locations: an Asian semi-final will be also be held during the Asian Test Symposium.

Because of ATS being held after ITC, the Asian semi-final for the 2015 TTTC’s E. J. McCluskey Doctoral Thesis Award will be held during the 2014 ATS, held in November 2014, and inscriptions are OPEN NOW.

For more information, please contact the Asian Local Coordinator Jiun-Lang Huang

All active doctoral students working on test-related topics and recent graduates who graduated 2013 or later are eligible for the Award. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results. Prospective contestants submit a summary of their thesis work (up to 2000 words), possibly accompanied by one additional page of figures and references. They are free to submit up to three published referenced as supporting material, which are considered by the jury on an optional basis. The abstract should clearly address the following:

  • define the problem and its relevance to industry,
  • describe existing industrial practices for solving the problem, and
  • explain the proposed methodology (and any pertinent case study) and how it advances the theory and/or practice in the particular field.

A student can freely choose the regional (semi-finals) site to submit the summary. Submissions to multiple regional sites are prohibited.

The 4 semi-finals sites for the Best Doctoral Thesis Award 2015:

  1. VLSI Test Symposium 2015 (VTS’15), local coordinator Ke Huang
  2. European Test Symposium 2015 (ETS’15), local coordinator Jaan Raik
  3. Latin Americ Test Symposium 2015 (LATS’15), local coordinator  José Lipovetzky
  4. Asian Test Workshop 2014 (ATS’14), 16-19 November 2014, Hangzhou, China.

Direct your questions to Michele Portolan (Université Grenoble Alpes, France).

Based on the submitted abstracts, a set of semi-finalists will be selected for the semi-finals of the contest. Semi-finals could be canceled if the numbers of submissions is inadequately low, in which case candidates will be invited to take part in another semi-final. This round includes a short (seven-minute) slot for oral presentation during a dedicated session at the semi-final event. The jury will judge the presentations, and the winner of the semi-final will be announced during the event. The finalists will present their work in a 30-minute presentation at ITC’15, and the winner will be determined by a panel of industrial experts. The Award is given to the winning student and the advisor of the thesis.

2014 Award Winner: Samah Saeed

Organization and coordination

Global Coordinator: Michele Portolan (Université Grenoble Alpes, France).

North American contest coordinator: Michail Maniatakos (NYUAD, UAE).

South American contest coordinator: Paolo Rech (UFRGS, Brazil).

Europe contest coordinator: Jaan Raik (Tallin University, Estonia).

Past recipients

Name Year Description Location
Samah Saeed,
NYU Polytechnic
School of Engineering
2014 1st Place Winner. Thesis Topic: “DfT Approaches and Security Challenges in the Scan Design” ITC 2014
Julio César Vázquez Hernández,
National Institute for Astrophysics
Optics and Electronics (INAOE)
2014 Runner Up. Thesis Topic: “Aging Robust Monitoring and Techniques to Improve Performance on Digital Systems” ITC 2014
Luca Cassano,
University of Pisa
2014 Runner Up. Thesis Topic: “Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs” ITC 2014
Louay Abdallah,
Université Grenoble Alpes
2013 1st Place Winner. Thesis Topic: “Non-intrusive embedded sensors for RF circuit test” ITC 2013
Ke Huang,
Université Grenoble Alpes
2013 2nd Place Winner. Thesis Topic: “Fault Modelling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits” ITC 2013
Suraj Sindia,
Auburn University
2013 3rd Place Winner. Thesis Topic: “High sensitivity test signature for unconventional analog circuit test paradigms” ITC 2013
Wing Chiu Tam,
Carnegie Mellon University
2011 1st Place Winner. Thesis Topic: “Physically-Aware Analysis of Systematic Defects in Integrated Circuits” ITC 2011
Guihai Yan,
ICT Beijing
2011 2nd Place Winner. Thesis Topic: “Online Timing Variation Detection and Tolerance for Digital Integrated Circuits” ITC 2011
Urban Ingelsson,
University of Southampton, UK
2011 3rd Place Winner. Thesis Topic: “Investigation into Voltage and Process Variation-Aware Manufacturing Test” ITC 2011
Stephan Eggersgluess,
University of Bremen
2010 1st Place Winner. Thesis Topic: “Robust Algorithms for High Quality Test Pattern Generation using Boolean Satisfiability” ITC 2010
Hsiu-Ming (Sherman) Chang,
University of California,
Santa Barbara
2010 2nd Place Winner. Thesis Topic: “Low-Cost Quality Assurance Techniques for High-Performance Mixed-Signal/RF Circuits and Systems” ITC 2010
Alex Roschildt Pinto,
Universidade Federal de
Santa Catarina, Brazil
2010 3rd Place Winner. Thesis Topic: “Autonomic Methods for Enhancing Communication Quality of Service in Dense Wireless Sensor Networks with Real Time Requirements” ITC 2010
Mahmut Yilmaz,
Duke University
2009 1st Place Winner. Thesis Topic: “Automated Test Grading And Pattern Selection for Small-Delay Defects” VTS 2009
Erkan Acar,
Duke University
2009 2nd Place Winner. Thesis Topic: “Architectural and Defect-Based Test and Diagnosis Techniques for RF Integrated Circuits” VTS 2009
Bo Yang,
Polytechnic Institute of NYU
2009 3rd Place Winner. Thesis Topic: “Design-for-Test Techniques for Securing Scan-based Designs” VTS 2009
Devanathan Varadarajan,
Indian Institute of Technology,
Madras, India
2008 First Place Winner. Thesis Topic: “On Power-safe Testing of System-on-Chips” VTS 2008
Sudarshan Bahukudumbi,
Duke University, USA
2008 Second Place Winner. Thesis Topic: “Wafer-Level Testing and Test Planning for Integrated Circuits” VTS 2008
Francois-Fabien Ferhani,
Stanford University, USA
2008 Third Place Winner. Thesis Topic: “Comparing Partial and Complete Test Sets and Test Metrics” VTS 2008
Nisar Ahmed,
University of Connecticut, USA
2007 First Place Winner. Thesis Topic: “High Quality Delay Tests for Very Deep Submicron Designs” VTS 2007
Nikola Bombieri,
University of Verona, Italy
2007 Second Place Winner. Thesis Topic: “A TLM Design for Verification Methodology” VTS 2007
Ahcene Bounceur,
TIMA Laboratory,
Grenoble, France
2007 Third Place Winner. Thesis Topic: “CAT Platform for Mixed-Signal Circuit Testing” VTS 2007
Federico di Palma,
University of Pavia, Italy
2006 First Place Winner. Thesis Topic: “End-of-line Algorithms for Process Diagnosis in Semiconductor Manufacturing” VTS 2006
Achraf Dhayni,
TIMA Laboratory,
Grenoble, France
2006 Second Place Winner. Thesis Topic: “Pseudorandom Built-In Self-Test for MEMS” VTS 2006
Paolo Bernardi,
Politecnico di Torino, Italy
2006 Third Place Winner. Thesis Topic: “Test Techniques for Systems on a Chip” VTS 2006
Alberto Valdes-Garcia 2005 First Place Winner. Thesis Topic: “Development and Implementation of Built-In Testing Techniques for Analog and RF Integrated Circuits” VTS 2005
Anand Gopalan 2005 Second Place Winner. Thesis Topic: “Built-In-Self-Test of RF Front-end Circuitry” VTS 2005
Haralampos Stratigopoulos 2005 Third place co-winner. Thesis Topic: “Neural Classification of Analog Circuits” VTS 2005
Swarup Bhunia 2005 Third place co-winner. Thesis Topic: “Novel Low-Overhead Design-For-Testability Techniques for Improving Testability in Nano-Scaled Circuits” VTS 2005