The Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. The Award is given to the winner of a two-stage contest with semi-finals held at TTTC-sponsored conferences, symposia or workshops. The winners of the semi-finals, determined by jurys composed of industrial experts, will compete against each other in the finals, held at a major TTTC-sponsored conference or symposium. This major Award is named after Prof. Edward J. McCluskey, a key educator and mentor in the fields of test technology, logic design, and reliability.
Call for Participation 2022
We are happy to announce that in 2022, the Contest will be coming held in 4 locations: the Asian Test Symposium, the European Test Symposium, the Latin-America Test Symposium and the VLSI Test Symposium
Because of ATS is held after or really close to ITC, the Asian a semi-final for the TTTC’s E. J. McCluskey Best Doctoral Thesis Award will be held in 2021.
All active doctoral students working on test-related topics and recent graduates who graduated in 2020 or later are eligible for the Award. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results.
Prospective contestants submit a summary of their thesis work (up to 2000 words), possibly accompanied by one additional page of figures and references. They are free to submit up to three published referenced as supporting material, which are considered by the jury on an optional basis. The abstract should clearly address the following:
- define the problem and its relevance to industry,
- describe existing industrial practices for solving the problem, and
- explain the proposed methodology (and any pertinent case study) and how it advances the theory and/or practice in the particular field.
- A student can freely choose the regional (semi-finals) site to submit the summary. Submissions to multiple regional sites are prohibited.
The 4 semi-finals sites for the Best Doctoral Thesis Award 2022:
- VLSI Test Symposium 2022, (VTS’22), local coordinator Ujjwal Guin
- European Test Symposium 2022 (ETS’22), local coordinators Alessandro Savino, Alberto Bosio
- Latin Americ Test Symposium 2022 (LATS’22), local coordinator TBD
- Asian Test Symposium 2021 (ATS’21), local coordinator Hiroshi Takahashi
For submission information, please refer to the Local Coordinator at the conference website. Each Semi-Final has its own local rules: please refer to the Local Coordinator for detailed submission instructions.
For general inquiries, direct your questions to the Global Coordinator, Michele Portolan (Grenoble-INP, France).
Based on the submitted abstracts, a set of semi-finalists will be selected for the semi-finals of the contest. Semi-finals could be canceled if the numbers of submissions is inadequately low, in which case candidates will be invited to take part in another semi-final. Each Semi-Final has its own local rules: please refer to the Local Coordinator for detailed submission instructions. This round usually includes a short (seven-minute) slot for oral presentation during a dedicated session at the semi-final event. The jury will judge the presentations, and the winner of the semi-final will be announced during the event.
The finalists will be invited to submit a summary of their thesis to be included in the ITC’22 Proceedings, and present their work in a dedicated Session. The winner will be determined by a panel of academic and industrial experts. The Award is given to the winning student and the advisor of the thesis.
|Lizhou Wu||Delft University of Technology, Netherlands||2021||Winner||Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions|
|Mengyun Liu||Duke University, USA||2021||Finalist||Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards|
|Foisal Ahmed||Nara Institute of Science and Technology (NAIST), Japan||2021||Finalist||Study on High-Accuracy and Low-Cost Recycled FPGA Detection|
|Mohammad Nasim Imtiaz Khan||The Pennsylvania State University, USA||2020||Winner||Assuring Security and Reliability of Emerging Non-Volatile Memories|
|Sarah Azimi||Politecnico di Torino, Italy||2020||Finalist||Digital Design Techniques for Dependable High Performance Computing|
|Rajit Karmakar||Department of E&ECE, Indian Institute of Technology Kharagpur, India||2020||Finalist||Hardware IP Protection Using Logic Encryption and Watermarking|
|Rafael B. Schvittz||Federal University of Pelotas – UFPEL, Brazil||2020||Finalist||Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients|
|Tao Chen||Iowa State University, USA||2019||Winner||Thesis title: Built-in Self-Test and Self-Calibration for Analog and Mixed Signal Circuits|
|Innocent Okwudili||Delft University of Technology, Netherlands||2019||Finalist||Reliability Modeling and Mitigation for Embedded Memories|
|Francisco E. Rangel-Patiño||The Jesuit University of Guadalajara, Mexico||2018||Winner||Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation|
|Muhammad Yasin||New York University Tandon School of Engineering||2018||Finalist||Towards Provably Secure Logic Locking for Hardening Hardware Security|
|Justyna Zawada||Poznań University of Technology, Poland||2018||Finalist||On New Class of Test Points and Their Applications|
|Fakir Sharif Hossain||Graduate School of Information Science Department of Computer Science and Engineering Nara Institute of Science and Technology, Japan||2018||Finalist||Variation-Aware Hardware Trojan Detection through Power Side-channel|
|Yuming Zhuang||Iowa State University||2017||Winner||Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements|
|Surajit Kumar Roy||Indian Institute of Engineering Science and Technology||2017||Finalist||Design-for-Test and Test Optimisation for 3D SOCs|
|Boyang Du||Politecnico di Torino||2017||Finalist||Fault-tolerant Electronic System Design|
|Ran Wang||Duke University||2016||Winner||Testing of Interposer-Based 2.5D Integrated Circuits|
|Eduardo Chielle||Federal University of Rio Grande Do Sul (UFGRS)||2016||Finalist||Selective Software-Implemented Hardware Fault Tolerance Techniques to Detect Soft Errors in Processors with Reduced Overhead|
|Panagiota Papavramidou||Université Grenoble Alpes, TIMA Lab||2016||Finalist||Memory repair architectures for high defect densities|
|Lien Wei-Cheng||Dept. of Electrical Engr., National Cheng Kung University, Taiwan||2016||Finalist||Output bit selection methodology for test response compaction|
|Fabian Oboril||KIT Karlsruhe||2015||Winner||Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocess|
|Sergej Deutsch||Duke University||2015||Finalist||Test and Debug Solutions for 3D-Stacked Integrated Circuits|
|Li Jiang||The Chinese University of Hong Kong||2015||Finalist||Yield and reliability enhancement for 3D ICs|
|Samah Saeed||NYU Polytechnic School of Engineering||2014||Winner||DfT Approaches and Security Challenges in the Scan Design|
|Luca Cassano||University of Pisa, Italy||2014||Finalist||Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs|
|Julio César Vázquez Hernández||National Institute for Astrophysics Optics and Electronics (INAOE), Mexico||2014||Finalist||Aging Robust Monitoring and Techniques to Improve Performance on Digital Systems|
|Louay Abdallah||Université Grenoble Alpes, TIMA Lab||2013||Winner||Non-intrusive embedded sensors for RF circuit test|
|Suraj Sindia||Auburn University, Alabama, AL, USA||2013||Finalist||High sensitivity test signature for unconventional analog circuit test paradigms|
|Ke Huang||Université Grenoble Alpes, TIMA Lab||2013||Finalist||Fault Modelling and Diagnosis for Nanometric Analog/Mixed-Signal/RF Circuits|
|Nathan Kupp||Yale University||2012||Winner||Integrated Optimization of Semiconductor Manufacturing: A Machine Learning Approach|
|Darius Szysz||TU Poznan||2012||Finalist||Low power test application with selective compaction in VLSI designs|
|Wing-Chiu Tam||Carnegie Mellon University, USA||2011||Winner||Physically-Aware Analysis of Systematic Defects in Integrated Circuits|
|Urban Ingelsson||University of Southampton, UK||2011||Finalist||Investigations into Voltage and Process Variation-Aware Manufacturing Test|
|Guihai Yan||ICT Bejing||2011||Finalist||Online Timing Variation Tolerance for Digital Integrated Circuits|