Technical Activity Committee on HARDWARE SECURITY AND TRUST

TAC Chair:	Jim PLUSQUELLIC, jimp@ece.unm.edu
TAC Vice-Chairs:	Mohammad TEHRANIPOOR, tehrani@engr.uconn.edu Giorgio DI NATALE, giorgio.dinatale@lirmm.fr

Introduction

A wide range of applications, from secure RFID tagging to high-end trusted computing, relies on dedicated and trusted hardware platforms. The security and trustworthiness of such hardware designs are critical to their successful deployment and operation. Recent advances in tampering and reverse engineering show that important challenges lie ahead. For example, secure electronic designs may be affected by malicious circuits, Trojans that alter system operation. Furthermore, dedicated secure hardware implementations are susceptible to novel forms of attack that exploit side-channel leakage, faults, or test infrastructures. Third, the globalized, horizontal semiconductor business model raises concerns of trust and intellectual-property protection.

Topics

• Trojan Detection and Isolation
• Side channel Attacks and Countermeasures
• Fault-based Attacks and Countermeasures
• Intellectual Property Protection and Metering
• Tools and Methodologies for Secure Hardware Design
• Hardware Architectures for Cryptography
• Hardware Security Primitives: PUFs and TRNGs
• Trusted Platform and System Level Hardware Security
• Interaction of Secure Hardware and Software
• Non-destructive Reverse Engineering
• CAD Tool Security and Trust
• Supply Chain Security
• Test and Security

 Related Events

• HOST: IEEE International Symposium on HARDWARE-ORIENTED SECURITY and TRUST
• IOLTS (Topics: Secure circuit design, Fault-based attacks and counter measures)
• DATE: Conference on Design, Automation and Test in Europe
• VTS’2011 (Session 4b: Security)
• VTS’2010 (Special Session 11B: Hot Topic: Hardware Security: Design, Test and Verification Issues)
• VTS’2009 (Session 11B: Emergent Technology and Security
• Tutorials on Test and Security (LATW’09, ETS’09, DDECS’10)