High Level D&T

Technical Activity Committee on HIGH-LEVEL DESIGN AND TEST

This high-level design and test TAC was formed in 1995 with the aim of stimulating research and discussions on test and validation methodologies for ICs and systems specified using high level descriptions, where high-level refers to register-transfer, behavioral, and system level specifications.

The TAC has held annual workshops (IEEE High-Level Design Validation and Test 1996-2002) on the topic. The TAC has also been active in organizing technical sessions at various TTTC sponsored meetings.

The goal of the TAC, and the HLDVT workshops, is to provide an informal forum, bringing together designers and test and validation researchers working in validating, debugging, and testing designs in an effort to address high-level design validation and test issues concurrently.

While the TAC itself has not been particularly active in recent years, the HLDVT workshop continues to thrive. For those interested in pursuing this subject, there are several very active areas to pursue, including the SystemC project and the open-source TestBuilder project (which is sponsored by Cadence Design Systems).

Upcoming conferences and symposia

IEEE VLSI Test Symposium (VTS) 2026
Submission deadline: December 5, 2025
Notification: January 24, 2026
Camera-ready upload: February 28, 2026
Conference: April 27-29, 2026

IEEE European Test Symposium (ETS) 2026
Submission of title, abstract, authors: 15 December 2025
Full paper submission: 12 January 2026
Notification of acceptance: 20 February 2026
Camera-ready manuscript: Deadline: 22 March 2026
Conference: May 25-29, 2026

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2026

Submission of title, abstract, and authors: March 1, 2026
Final Paper Submission: March 8, 2026
Author Notification: April 12, 2026
Conference Dates: July 1 – 3, 2026

International Test Conference (ITC) 2026
Paper title/abstract due: March 20, 2026
Paper final PDF due: April 24, 2026
Author notification: June 19, 2026
Conference Dates: October 11 to 16, 2026

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) 2026
Title and abstract submissions April 24th, 2026
Full paper submissions May 1st, 2026
Notification July 10th, 2026
Camera ready and author’s registration July 24th, 2026