Board Test

Technical Activity Committee on Board Test

TAC Chair:  Bill EKLOW, beklow@cisco.com

The TTTC Board Test Technical Activities Committee (BTTAC) is the successor to the Board Test Action Group (BTAG). The original purpose of BTAG was to identify a group of board test professionals to help bring back board test into the International Test Conference (ITC).

We also started an IEEE Board Test Workshop (BTW). The first two BTWs were run in conjunction with ITC 2002 and 2003 and attracted between 50 and 60 attendees.

In addition, we have established an e-mail reflector and a message chat room that allows information on board test activities to be disseminated and also is beginning to work as a “has anyone seen this problem and knows of a solution?” informal Q&A “chat room”.

We recently polled the members of BTAG (some 55 people at the moment) on the future role of BTAG. The basic question was “should we continue?”. We received a resounding “yes” to this question with suggestions that the role of BTAG could expand in the following areas, at least:

  • Provide a forum for emerging new problems, issues, solutions and concepts in board test, including:
    • Resolving issues with new Standards e.g. IEEE 1149.6, adoption of 1149.5 (why did it fail?)
    • Fostering the creation of new Standards (IEEE, JEDEC, etc)
    • Education e.g. the issues surrounding the new PICMG 3.0 Advanced TCA
  • Initiate and nurture board and system test activities (papers, panels, tutorials, etc) at international events such as ITC, DATE, BTW, ATS (Asian Test Symposium), etc
  • Keep on working with ITC PC and SC members to “bring back board test” by targeted solicitation of papers, panels, tutorials and help for the novitiates and neophytes.

These are the activities that will be fostered under the new BTTAC umbrella.

If you have questions, comments or just want to join this Board Test Technical Activities Committee, send e-mail to Bill EKLOW

Upcoming conferences and symposia

IEEE VLSI Test Symposium (VTS) 2026
Submission deadline: December 5, 2025
Notification: January 24, 2026
Camera-ready upload: February 28, 2026
Conference: April 27-29, 2026

IEEE European Test Symposium (ETS) 2026
Submission of title, abstract, authors: 15 December 2025
Full paper submission: 12 January 2026
Notification of acceptance: 20 February 2026
Camera-ready manuscript: Deadline: 22 March 2026
Conference: May 25-29, 2026

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2026

Submission of title, abstract, and authors: March 1, 2026
Final Paper Submission: March 8, 2026
Author Notification: April 12, 2026
Conference Dates: July 1 – 3, 2026

International Test Conference (ITC) 2026
Paper title/abstract due: March 20, 2026
Paper final PDF due: April 24, 2026
Author notification: June 19, 2026
Conference Dates: October 11 to 16, 2026

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) 2026
Title and abstract submissions April 24th, 2026
Full paper submissions May 1st, 2026
Notification July 10th, 2026
Camera ready and author’s registration July 24th, 2026