Technical Activity Committee on POWER-AWARE TESTING
| TAC Chair | Patrick GIRARD, girard@lirmm.fr |
| TAC Co-Chair | Xiaoqing WEN, wen@cse.kyutech.ac.jp |
Description
Power has become the dominating factor in VLSI design and the biggest driving force in the semiconductor industry. This has made low-power design one of the hottest research and development topics, resulting in a growing number of hardware/software-based techniques for drastically reducing functional power dissipation. However, testing such low-power VLSI circuits has increasingly become a severe challenge. The first reason is that test power can be several times higher than functional power, and excessive test power causes die/package damage due to excessive heat as well as undue yield loss due to excessive power supply noise. The second reason is that a low-power VLSI design contains unconventional structures for power management, which, if not thoroughly tested, will severely compromise product quality. Clearly, low-power VLSI designs cannot be successfully realized without effective and efficient power-aware testing techniques.
Based on this background, the proposed technical activity committee intends to vigorously promote research and development in power-aware testing.
Topics
- Power analysis
- Power Safety Checking
- Power-Aware Test Generation
- Power-Aware DFT
- Power-Aware BIST
- Power-Aware Test Data Compression
- Fault Diagnosis and Silicon Debug of Low-Power Designs
- Test of Multi-Voltage Designs
- Test of Gated-Clock Designs
- Test of Power-Management Structures
- System-Level Power-Aware Test Scheduling
- Power-Aware On-Line Testing
- Power-Aware 3D Testing
- Power-Aware Fault Tolerance
- Power-Aware FPGA Testing
- IP with Embedded Power-Aware Test Infrastructure
Related Books
Related Books
- Power-Aware Testing and Test Strategies for Low Power Devices (Springer, New York, 2009)
Related Journals
- IEEE Design & Test of Computers
- Most of IEEE Transactions journals (TVLSI, TC, TCAD, TODAES, …)
Related Events
- LPonTR (IEEE Int’l Workshop on the Impact of Low-Power Design on Test and Reliability)
- DATE (Conference on Design, Automation and Test in Europe)
2008 (Hot Topic Session: Test Challenges for Low Power Devices) - VTS (VLSI Test Symposium)
2010 (Panel: Low-Power Test and Noise-Aware Test: Foes or Friends?) - ATS (Asian Test Symposium)
2009 (Panel: Is Low Power Testing Necessary? What does the Test Industry Truly Need?) - IGCC-WS (International Green Conference on Computing – Low-Power SoC Workshop)
2011 (Special Session on Low-Power Testing) - WRTLT (International Workshop on RTL and High Level Testing)
2008 (Panel: Roads to Power-Safe LSI Testing) - ITC (International Test Conference), ETS (European Test Symposium)
Numerous regular sessions on this topic - Tutorials:
- Power-Aware Testing and Test Strategies for Low Power Devices (DATE’08, ITC’09, ATS’09, LATW’10, NEWCAS’10, MWSCAS’ 10, ICM’10, DATE’11, ITC’11)
- Power Issues in Test (ETS’07)