THE TTTC JAMES BEAUSANG STUDENT AWARD FOR DFT

THE TTTC JAMES BEAUSANG STUDENT AWARD FOR DFT

To encourage student participation and recognize excellence in the field of design for testability, the IEEE Computer Society Test Technology Technical Council (TTTC) established the TTTC James Beausang Student Award for DFT.

This Award honors the memory of Dr. James Beausang, a well-known researcher and practitioner in Design for Testability and Test Synthesis. The Award endowment came from private, corporate and IEEE funding.

The TTTC Beausang Award was granted exclusively to undergraduate or graduate student(s) listed as primary authors of a qualifying paper. Only papers accepted at the VLSI Test Symposium or the International Test Conference qualify. The paper content may be derived from university or industrial research and development. Eligible subject areas include test architectures, synthesis and analysis research applied to Scan, Design for Testability, Test Synthesis, BIST, Boundary Scan and Embedded Core Test. The Award was granted four times: VTS 1999, ITC 1999, VTS 2000, and ITC 2000.

Winners of the Award were:

  • VTS-1999: Hyungwon Kim, University of Michigan – Lead author of the paper H. Kim and J. P. Hayes, “Delay Fault Testing of Designs with Embedded IP Cores”
  • ITC-1999: Jayabrata Ghosh-Dastidar, University of Texas at Austin , Lead author of the paper J. Ghosh-Dastidar, D. Das and N. Touba, “Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information”
  • VTS-2000: Anshuman Chandra, Duke University, USA : “Test Data Compression for System-On-A-Chip using Gulomb Codes”
  • ITC-2000: Nicola Nicolici, University of Southampton, England, Lead author of the paper N. Nicolici and B. M. Al-Hashimi “Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths”

The Award benefits to the author(s) are:

  1. Recognition of the outstanding student achievement at the Plenary Session of the conference in the same year and in the TTTC Newsletter and other IEEE Publications
  2. A $500 check
  3. A Plaque or Certificate of Recognition
  4. Complementary registration in the following year at a TTTC Workshops: ITSW, ETW or TECS (other TTTC workshop access may also be arranged)
  5. Publication of a revised and extended version of the paper is made in IEEE Design & Test Magazine

For further information, please contact: Ken WAGNER

Upcoming conferences and symposia

IEEE VLSI Test Symposium (VTS) 2026
Submission deadline: December 5, 2025
Notification: January 24, 2026
Camera-ready upload: February 28, 2026
Conference: April 27-29, 2026

IEEE European Test Symposium (ETS) 2026
Submission of title, abstract, authors: 15 December 2025
Full paper submission: 12 January 2026
Notification of acceptance: 20 February 2026
Camera-ready manuscript: Deadline: 22 March 2026
Conference: May 25-29, 2026

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2026

Submission of title, abstract, and authors: March 1, 2026
Final Paper Submission: March 8, 2026
Author Notification: April 12, 2026
Conference Dates: July 1 – 3, 2026

International Test Conference (ITC) 2026
Paper title/abstract due: March 20, 2026
Paper final PDF due: April 24, 2026
Author notification: June 19, 2026
Conference Dates: October 11 to 16, 2026

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) 2026
Title and abstract submissions April 24th, 2026
Full paper submissions May 1st, 2026
Notification July 10th, 2026
Camera ready and author’s registration July 24th, 2026