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IEEE International Symposium on
Defect and Fault Tolerance in
VLSI and Nanotechnology Systems
CALL FOR PAPERS
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The topics include (but are not limited to) the following ones:
1. Yield Analysis and Modeling
2. Testing Techniques
3. Error Detection, Correction, and Recovery
4. Dependability Analysis and Validation
5. Defect and Fault Tolerance
6. Design For Testability in IC Design
7. Repair, Restructuring and Reconfiguration
8. Totally Fail-Safe Design for Critical
9. Emerging Technologies
10. Hardware security
Prospective authors are invited to submit original and unpublished contributions (6 pages - with the opportunity to purchase 2 additional ones - in the IEEE conference template, 2-columns style, available on conference web site), to be submitted as PDF file. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:
We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.
Paper Publication and Author Registration: Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library.
Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the proceedings. The author is also expected to attend the Symposium and present the paper.
Best Student Paper Award: All papers with a student as both primary author and presenter will be taken into consideration for the 2012 Best Student Paper Award, sponsored by Intel.
Journal Special Issue: There will be a possibility for the authors of selected papers presented at DFT 2012 to submit an extended version of their work in a special issue of an archival journal.
Submission deadline: May 6, 2012
Technical Program Committee
For more information, visit us on the web at: http://www.dfts.org
The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
1ST VICE CHAIR
ITC GENERAL CHAIR
EAST & AFRICA
PRESIDENT OF BOARD
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC