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TTTC's
Electronic Broadcasting Service |
3rd IEEE International Workshop on Reliability Aware System Design and Test
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CALL
FOR PAPERS |
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Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore’s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems. Representative topics include, but are not limited to:
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Authors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 6 to 7 keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission via workshop website http://www.serc.iisc.ernet.in/~viren/RASDAT12/ Submissions are due no later than October 21, 2011. Authors will be notified of the disposition of their presentation by November 15, 2011 Authors of accepted presentations must submit the final paper by December 1, 2011 for inclusion in the Workshop Proceedings, which will be provided to the attendees. |
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Submission deadline: October 21, 2011 |
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Additional Information | |||
General Information Adit Singh Virendra Singh Program Related Information
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Committees | |||
Organizing Committee General Co-Chairs General Vice Co-Chairs Program Co-Chairs Program Vice Co-Chairs Organizing Committee Co-Chairs Publication Chair Finance Co-Chair Publicity Chair Local Arrangement Chair Website Management Chair Registration Chair Steering Committee K.K. Saluja (US) – Chair Program Committee TBD |
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For
more information, visit us on the web at: http://www.serc.iisc.ernet.in/~viren/RASDAT12/ |
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The 3rd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
IEEE
Computer Society- Test Technology Technical Council |
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TTTC
CHAIR PAST
CHAIR TTTC
1ST VICE CHAIR SECRETARY ITC GENERAL CHAIR TEST
WEEK COORDINATOR TUTORIALS
AND EDUCATION STANDARDS EUROPE MIDDLE
EAST & AFRICA STANDING
COMMITTEES ELECTRONIC
MEDIA |
PRESIDENT OF BOARD SENIOR
PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL
MEETINGS TECHNICAL
ACTIVITIES ASIA
& PACIFIC LATIN
AMERICA NORTH
AMERICA COMMUNICATIONS INDUSTRY
ADVISORY BOARD |