TTTC Header Image
TTTC's Electronic Broadcasting Service

IEEE International High-Level Design, Validation and Test Workshop
(HLDVT 2008)

Nov. 19-21, 2008
Lake Tahoe, NV, USA

http://www.hldvt.com/08

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

top

IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level. The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, synthesizing, and testing designs specified using high level descriptions, in an effort to address high level design, validation, and test issues concurrently.

Key Dates
top

Advance Discounted Registration Deadline: October 16, 2008
Online Registration Deadline: November 14, 2008

The Venue
top

Discover an alpine paradise at Hyatt Regency Lake Tahoe Resort, Spa and Casino. Nestled within the Sierra Mountain Range, the stunning locale of this Four Diamond Lake Tahoe hotel is the ideal setting for year-round pampering. Take a cruise on one of the resort’s private boats, then tempt Lady Luck in the Casino. Ease tired muscles with a deep-tissue massage in the world-class spa, or bask in the sunshine on the private beach. Reconnect with family – and yourself – while enjoying the natural wonders in and around the remarkable Lake Tahoe, Nevada hotel. From delicious cuisine and inviting guestrooms to luxurious amenities and services, you'll experience an incomparable mountain escape at the Hyatt hotel in Lake Tahoe.

Hotel Regisration: http://www.laketahoe.hyatt.com/hyatt/hotels/rooms

Register online: HLDVT Group Code: G-IEEE http://www.laketahoe.hyatt.com/

Hotel rates - Single/ Double $140.00

Hotel Address

Hyatt Regency Lake Tahoe Resort, Spa and Casino
111 Country Club Drive,
Incline Village, Nevada, USA 89451
Tel: +1 775 832 1234    Fax: +1 775 831 2171
Workshop Registration
top

Full Conference Registration includes the hard copy proceedings, the banquet dinner on Thursday, November 20, 2008.

If you would like to bring a guest to the banquet dinner with you a guest banquet ticket may be added to your registration.

Register online with a major credit card, Visa, MasterCard or American Express Only.

Register by Mail with a check or Register by Fax with a major credit card: Visa, MasterCard or American Express Only.

MP Associates, Inc.
5405 Spine Rd. Ste. 102
Boulder, CO 80301
Fax: 303-530-4334

ONLINE REGISTRATION
Click Here


 
ADVANCE RATE OCT. 16
LATE RATE AFTER OCT. 16
Full Conference IEEE Member
$440
$555
Full Conference Non-Member
$555
$690
Student IEEE Member
$275
$350
Student Non-Member
$325
$395

Guest Banquet Dinner
$100

Refund/Cancellation Policy: Written requests for cancellations must be received on or before October 16, 2008, and are subject to a $50 processing fee. Cancellations received after October 16, 2008, will NOT be honored and all registration fees will be forfeited.

Advance Program
top

Wednesday -- Thursday -- Friday

November 19, 2008 (Wednesday)
 
6:00 PM - 8:00 PM REGISTRATION
 
November 20, 2008 (Thursday)
 
7:30 AM - 5:00 PM REGISTRATION
 
7:30 AM - 8:20 AM CONTINENTAL BREAKFAST
 
8:20 AM - 8:30 AM WELCOME ADDRESS
 
8:30 AM - 9:45 AM Session 1 - SOC VERIFICATION METHODOLOGIES
 

Positioning Test-Benches and Test - Programs in Interaction-Oriented System-on-Chip Verification
Xiaoxi Xu, Cheng-Chew Lim and Michael Liebelt - Univ. of Adelaide, Australia

 

A Method for Hunting Bugs that Occur Due to System Conflicts
Daniel Geist and Oded Vaida - Intel Corp., Haifa, Israel

 

Applications of Observer and Decorator Design Patterns in SoC Verification
Farzin Karimi - Metronome, Inc.

 
9:45 AM - 10:00 AM BREAK
 
10:00 AM - 10:50 AM Session 2 - TEST
 

A BIST Scheme for Full Characterization of ADC Parameters in Mixed-Signal SoCs
Chao Yuan, Yuanfu Zhao and Jun Du - Beijing Microelectronics Technology Institute

 

Test Slice Difference Technique for Low Power Encoding
Wei-Lin Li, Tsung- Tang Chen, Po-Han Wu and Jiann-Chyi Rau -Tamkang Univ., Taiwan R.O.C.

 
10:50 AM - 11:00 AM BREAK
 
11:00 AM - 12:30 PM Session 3 - Panel: SOFTWARE PRACTICES FOR VERIFICATION/ TESTBENCH MANAGEMENT
Moderator: 
Shireesh Verma - Conexant Systems, Inc.
 

Participants:

Mark Glassar - Mentor Graphics, Inc.
Badri Gopalan - Synopsys, Inc.
Srinath Atluri - Cisco Systems, Inc.
Sharon Rosenberg - Cadence Design Systems
Valeria Bertacco - Univ. of Michigan

 
12:30 PM - 2:00 PM LUNCH
 
2:00 PM - 3:40 PM Session 4 - FORMAL VERIFICATION
 

On Dynamic Switching of Navigation for Semi-Formal Design
Ankur Parikh and Michael Hsiao - Virginia Tech., USA

 

Multi-Level Bounded Model Checking to Detect Bugs Beyond the Bound
Tasuku Nishihara, Takeshi Matsumoto and Masahiro Fujita - Univ. of Tokyo

 

Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving
Katell Morin-Allory - TIMA, France, Marc Boulé - McGill Univ., Canada
Dominique Borrione - TIMA, France, Zeljko Zilic - McGill Univ., Canada

 

Janus: A Novel Use of Formal Verification to do Targeted Behavioral Equivalence
Prakash Math and David Hoenig - Intel Corp., Hillsboro, OR, USA

 
3:45 PM - 3:55 PM BREAK
 
3:55 PM - 5:55 PM Session 5 - Invited Session: ON-CHIP INSTRUMENTATION FOR SILICON VALIDATION AND DEBUG
 

In-System Silicon Validation Using a Reconfigurable Platform
Miron Abramovici - DAFCA

 

On-Chip Instrument Application to SoC Analysis
Neal Stollon - HDL Dynamics, Inc.

 
7:00 PM - 10:00 PM BANQUET DINNER AND KEYNOTE ADDRESS
  Keynote Speaker: TBD
 
November 21, 2008 (Friday)
 
7:30 AM - 12:30 PM REGISTRATION
 
7:00 AM - 8:00 AM CONTINENTAL BREAKFAST
 
8:00 AM - 9:40 AM Session 6- FUNCTIONAL TESTING AND VERIFICATION
 

Test and Validation of a Non-Deterministic System - True Random Number Generator
Kapila Udawatta, Sergey Maidanov, Mehdi Ehsanian and Surya Musunuri - Intel Corp.

 

Functional Testing Approaches for BIFST-able tlm_fifo
Homa Alemzadeh - Univ. of Tehran, Iran
Stefano Di Carlo, Alberto Scionti and Paolo Prinetto - Politecnico de Torino, Italy
Zainalabedin Navabi - Univ. of Tehran, Iran

 

IBM System z Functional and Perf o rmance Verification Using X-Gen
Torsten Schober, Shimon Landa, Bodo Hoppe and Ronny Morad - IBM Corp.

 

Timing Verification of Distributed Network Systems at Higher Levels of Abstraction
Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi and Shaahin Hessabi - Sharif Univ. of Technology, Tehran

 
9:40 AM - 9:50 AM BREAK
 
9:50 AM - 11:05 AM Session 7- SIMULATION
 

Temporal Parallel Gate-level Timing Simulation
Dusung Kim and Maciej Ciesielski - Univ. of Massachusetts, Amherst
Kyuho Shim and Seiyang Yang - Pusan National Univ., Korea

 

The Role of Parallel Simulation on Functional Verification
Giuseppe Di Guglielmo, Franco Fummi - Univ. of Verona, Italy
Mark Hampton - Certess, France
Graziano Pravadelli and Francesco Stefanni - Univ. of Verona, Italy

 

A HW/SW Co-Simulation Framework for the Verification of Multi-CPU Systems
Stefano Cordibella, Franco Fummi, Giovanni Perbellini and Davide Quaglia - Univ. of Verona, Italy

 
11:05 AM - 11:15 AM BREAK
 
11:15 AM - 12:35 PM Session 8 - Panel: SOC POWER MANAGEMENT IMPLICATIONS ON VALIDATION AND TESTING
Moderator: Bhanu Kapoor - Mimasic
 

Participants:

John Goodenough - ARM
Manuel A d'Abreu - Sandisk Corp.
Shireesh Ve rma - Conexant Systems, Inc.
Kaushik Roy - Purdue Univ.
Shankar Hemmady - Synopsys, Inc.

 
12:35 PM - 2:00 PM LUNCH
 
2:00 PM - 3:30 PM Session 9 - Special Session: What's So Intelligent about Testbenches?
Organizer: Avi Ziv - IBM Corp.
 

Automatic Test Generation for Coverage Improvement
Chris Wilson - Nusym Technology, Inc.

 

Capturing Functional Intent in Intelligent Testbenches
Adnan Hamid - Breker Verification Systems

 

Why Intelligent Verification Needs Functional Qualification
Joerg Grosse - Certess

 
3:30 PM - 3:40 PM BREAK
 
3:40 PM - 4:30 PM Session 10 - COVERAGE AND METRICS
 

Optimized Coverage-Directed Random Simulation
Inigo Ugarte and Pablo Sanchez - Univ. of Cantabria, Spain

 

Evaluation of an Efficient Control-Oriented Coverage Metric
Kiran Ramineni, Shireesh Verma and Ian Harris - Univ. of California, Irvine

 
4:30 PM - 4:40 PM BREAK
 
4:40 PM - 5:55 PM Session 11 - DEFECT AND FAULT MODELS AND TEST
 

High-Level Vulnerability over Space and Time to Insidious Soft Errors
Kenneth Zick and John Hayes - Univ. of Michigan

 

Automating Defects Simulation and Fault Modeling for SRAMs
Stefano Di Carlo, Paolo Prinetto and Alberto Scionti - Politecnico de Torino, Italy
Zaid Al-Ars - Delft Univ. of Technology, The Netherlands

 

Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers
Daniel Gil, Luis J. Saiz, Joaquin Gracia, Juan C. Baraza and Pedro Gil - Univ. Politecnica de Valencia, Spain

 
More Information
top

General Information

Prab Varma
General Chair
E-mail:
generalchair@hldvt.com

Program Information

Priyank Kalla
Program Chair
E-mail:
programchair@hldvt.com

Advance Program: http://www.hldvt.com/08/advance_program.html
Registration Link: http://www.hldvt.com/08/registration.html
Hotel Information: http://www.hldvt.com/08/local.html
Home Page: http://www.hldvt.com/08/index.html

Committees
top

Organizing Committee

General Chair
Prab Varma, Blue Pearl Software

Program Chair
Priyank Kalla, Univ. of Utah

Past Chair
Michael Hsiao, Virginia Tech

Finance Chair
Li-C Wang, UCSB

Publications Chair
Prabhat Mishra, Univ. of Florida

Web Publicity Chair
Ismet Bayraktaroglu, Sun

Publicity Chair
Sandeep Bhatia, Cadence

Industry Liaison
Bob Beckwith, LSI Logic

Local Arrangements Chair
Hussain Al-Assad, UC Davis

Program Committee

Mark Aagaard, Univ. of Waterloo
Samar Abdi, UC Irvine
Valeria Bertacco, Univ. of Michigan
Pankaj Chauhan, Calypto
Tim Cheng, UC Santa Barbara
Farzan Fallah, Fujitsu Labs of America
Franco Fummi, Univ. di Verona
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Harry Hsieh, UC Riverside
Alan Hu, Univ. British Columbia
Robert Jones, Intel
Wolfgang Rosenstiel, T¨ubingen Univ.
Pablo Sanchez, Univ. of Cantabria
Sandeep Shukla, Virginia Tech
Lionel Torres, Univ. of Montpellier
Miroslav Velev, Aries Design Automation
Shireesh Verma, Marvell Tech
Jin Yang, Intel
Zeljko Zilic, McGill Univ.
Avi Ziv, IBM

Steering Committee

Bernard Courtois, CMP-TIMA
Sujit Dey, UC San Diego
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Blue Pearl Softwar

For more information, visit us on the web at: http://www.hldvt.com/08

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT2008 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Doug J. YOUNG
SV Probe Inc.
- USA
Tel.
E-mail dyoung@svprobe.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


This message contains public information only. You are invited to copy and distribute it further.

For more information contact the TTTC office or visit http://tab.computer.org/tttc/

To remove your name from this mailing list, please email unsubscribetttc@cemamerica.com or login to the TTTC Database and uncheck the EBS (Electronic Broadcast Service) box, which can modified by selecting "Edit" next to "My Subscriptions".