Monday -- Tuesday -- Wednesday
|9:00 am - 10:30
||Alex Orailoglu, General Chair
||Michael Campbell, Senior Vice President of Engineering, Qualcomm CDMA Technologies
||Peter Maxwell and Cecila Metra, Program Co-Chairs
||"A Revolution in Design and Test Technology," Prof. Melvin Breuer, University of Southern California
||TTTC Most Successful Technical Meeting Award
TTTC Most Populous Technical Meeting Award
VTS 2007 Best Paper Award
VTS 2007 Best Panel Award
VTS 2007 Best Innovative Practices Award
am - 12:00 pm
Session 1A: TESTING FOR HIGH SPEED
Moderator: B. Courtois – TIMA
1A.1 Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems
Q. Dou, J. Abraham – Univ. of Texas at Austin
1A.2 Test Enabled Process Tuning for Adaptive Baseband OFDM Processor
M. Nisar, A.
Chatterjee –Georgia Inst. of Tech.
1A.3 Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links
D. Hong, K.T. Cheng – Univ. of California,
Session 1B: COMPACTION FOR TESTING
Moderator: T. Williams – Synopsys
1B.1 How Many Test Patterns are Useless?
Ferhani – Stanford Univ., N. Saxena – NVIDIA,
E. McCluskey – Stanford CRC, P. Nigh – IBM
1B.2 Constructing Augmented Multimode Compactors
E. Gizdarski – Synopsys
1B.3 Increasing Output Compaction in Presence of Unknowns using an X-Canceling MISR with Deterministic Fault Detection
R. Garg, N. Touba – Univ. of Texas at Austin, R. Putman – Cirrus
IP Session 1C: HIGHWAYS TO ZERO-DEFECTS:
Organizers: A. K. Majhi – NXP
Moderator: D. Wu – Intel
Description: Critical products like automotive, aerospace and medical demand 0-defect silicon. This Innovative Practices session will address different approaches taken by some of the key semiconductor manufacturers to achieve zero-defects. The three presentations in this session, and their descriptions are given below.
1C.1 DFT Opportunities to achieve Zero Defects
Raina, L. Winemberg – Freescale
1C.2 Statistical Scan Diagnosis - new road to high quality
S. Eichenberger, C. Hora, J.
Geuzebroek, B. Kruseman, A. K. Majhi – NXP
1C.3 Extending Quality Beyond Time Zero Through Additional DFT and Test
S. K. Vooka, V.
Jayaram, R. Parekhji – Texas Instruments
pm - 2:20 pm
Session 2A: ATE DATA VOLUME AND FALSE/
ACCEPTABLE TEST FAILS
Moderator: E. Volkerink – Verigy
2A.1 Inconsistent Fails due to Limited Tester Timing Accuracy
I. Park, D. Lee – Stanford Univ., E.
Chmelar – LSI Logic, E. McCluskey - Stanford
2A.2 A Regression Based Technique for ATE-aware Test Data Volume Estimation of System-on-Chips (SoCs)
S. Ravi, R. Tiwari, A. Shrivastava,
M. Warhadpande, R. Parekhji – Texas
2A.3 Basing acceptable error-tolerant performance on significance-based error-rate (SBER)
Z. Pan, M. Breuer –Univ. of Southern California
Session 2B: TEST AND DIAGNOSIS OF SCAN
Moderator: B. Cory – Nvidia
2B.1 Diagnosis of Scan Clock Failures
Basturkmen, K. L. Lee, S. Venkataraman – Intel
2B.2 An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation
S. Chun, Y.
Kim, T. Kim, S. Kang – Yonsei Univ.
2B.3 On the Detectability of Scan Chain Internal Faults - An Industrial Case Study
F. Yang – Univ. of Iowa, S. Chakravarty, N.
Devta-Prasanna – LSI Logic, S. Reddy – Univ.
of Iowa, Irith Pomeranz – Purdue Univ.
IP Session 2C: DEVICE DEGRADATION AND
Organizers: J. W. Tschanz – Intel
Moderator: G. Eide – Magma
Description: In an era of increasing performance targets and ever more stringent power requirements, design margins are shrinking more than ever. It is therefore critical to be able to understand the factors which impact product reliability and to accurately predict their effects. Overestimate the impact of NBTI, HCI, and TDDB on the product, and critical performance or power is left on the table. Underestimate these effects and the product suffers an unacceptable failure rate. Further complicating this picture is the fact that the relative importance of these different degradation mechanisms can change drastically from one process generation to the next.
The three presentations in this session show how a combination of careful modeling combined with product measurement data is used to set the reliability guardbands that are used. The speakers will demonstrate their unique approaches towards reliability modeling and characterization, and give insight into the reliability testing and characterization challenges that lie ahead.
2C.1 Realistic Projections of Product Fmax and Vmin Shifts due to HCI, NBTI, and TDDB
A. Haggag – Freescale
2C.2 Comprehending NBTI at the Product Level
Reddy – Texas Instruments
2C.3 In-line Manufacturing Measurement of Infant Mortality Thermal Activation Energy
A. Vassighi – Intel
pm - 3:40 pm
Session 3A: MEMORY DIAGNOSIS AND
Moderator: M. Rodgers
3A.1 An SRAM Design-for-Diagnosis Solution based on Write Driver Voltage Sensing
Ney, P. Girard, S. Pravossoudovitch, A. Virazel – LIRMM, M. Bastian, V. Gouin – Infi neon
3A.2 An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-operation Dynamic Faults in Random Access Memories
G. Harutyunyan, V.
Vardanian – Virage Logic
3A.3 Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
N. Mojumder – Purdue Univ., S. Mukhopadhyay – Georgia Inst. of Tech., J. J. Kim, C.T. Chuang – IBM T. J. Watson Research Center, K. Roy – Purdue Univ.
Session 3B: SPECIAL SESSION
WHY NANOSCALE PHYSICS FAVORS
QUANTUM INFORMATION &
WHY COMPUTING IS POSSIBLE IN SPITE OF
Organizer: B. Courtois – TIMA
Moderator: B. Kaminska – Simon Fraser Univ.
I. Markov – Univ. of Michigan
J. Hayes – Univ. of Michigan
Description: As transistor dimensions approach atomic scale, quantum-mechanical effects such as tunneling and spin become important ingredients in accurate performance models of integrated circuits.
IP Session 3C: AUTOMATIC TEST
DEVELOPMENT FOR MIXED-SIGNAL/RF
Organizer: V. Zivkovic – NXP
Moderator: K. Arabi – Qualcomm
3C.1 ATPG for SerDes Testing on any ATE, Bench-Top, or Simulator
S. Sunter, A. Roy, G. Danialy – LogicVision
3C.2 Test Verification and Program Generation for Modular System-on-Chips with Mixed-Signal Cores
V. Zivkovic, R. Jonker – NXP
3C.3 Automating Test Development for Mixed-Signal and RF circuits - Can Current Test Help?
Manhaeve – Q-Star
|4:00 pm - 5:00 pm
Session 4A: MODELING AND TESTING FOR
Moderator: S. Venkataraman – Intel
4A.1 Gate Oxide Early Life Failure Prediction
T. W. Chen, K. Kim, Y. M. Kim, S. Mitra– Stanford Univ.
4A.2 Full Open Defects Under Tunnelling Leakage Current in Nanometric CMOS
D. A. Delgado, R.
Rodriguez-Montanes, J. Figueras – Universitat
Politècnica de Catalunya, S. Eichenberger, C.
Hora, B. Kruseman – NXP
4A.3 Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann,
S. Hellebrand – Univ. of Paderborn, H. J.
Wunderlich - Univ. of Stuttgart
Session 4B: LOW POWER SCAN TESTING
Moderator: C. Landrault – LIRMM
4B.1 Bounded Adjacent Fill for Low Capture Power Scan Testing
A. Chandra, R. Kapur – Synopsys
4B.2 Reducing Scan Shift Power at RTL
J. Dworak – Brown Univ., Y. Huang, X. Lin, W. T.
Cheng – Mentor Graphics
4B.3 Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes
J. Wu – National Chiao Tung Univ.
IP Session 4C: BRIDGING PRE-SILICON
VERIFICATION AND POST-SILICON
VALIDATION AND DEBUG
Organizers: E.J. Marinissen – NXP
Moderator: N. Nicolici – McMaster Univ.
Description: In this session, we discuss how to bridge the pre-silicon verification to post-silicon validation and debug. Can test patterns and test benches developed for verification be reused during validation? Can bugs identified in validation be confirmed again in the verification environment? How can the DfT infrastructure available on-chip for manufacturing test help with bridging pre-silicon verification and post-silicon validation and debug? Are the scan chains sufficient or do we need more on-chip support? Are there any other established test technologies that can aid the post-silicon validation process?
4C.1 Pre-Silicon Verification Perspective
A. Adir– IBM
4C.2 Post-Silicon Design-for-Debug Perspective
Abramovici, P. Bradley – DAFCA
4C.3 Post-Silicon Hardware/Software Co-Debug Perspective
B. Vermeulen, K. Goossens – NXP
|8:00 pm - 9:30 pm
Special Session 5A: SPECIAL SESSION
ROBUST DESIGN: TECHNIQUES AND
Organizer: M. Zhang – Intel
Moderator: Z. Navabi – Worcester Poly
Description: Relentless technology scaling presents a challenging task of designing reliable systems in the presence of transient, intermittent, and gradual errors. It is crucial for the design & test community to understand the origin and impact of these errors, methods to characterize, screen, and analyze them, as well as design techniques to mitigate them. In this session, the speakers will provide comprehensive reviews of these three aspects of the robust design challenges with different industry/academia perspectives. Discussion on error sources will focus on soft errors, process variation, and device degradation. Both theoretical modeling of these effects and experimental data from test chips will be presented. We will focus on logic and memory circuits for the design techniques to demonstrate the principles of robust design. A full-chip deployment strategy of such robust circuit elements will also be discussed. Experimental data and theoretical projection on sub-65nm technologies will be presented to illustrate the trend and potential new challenges for future technologies and motivate future robust design research.
K. Roy – Purdue Univ.
K. Agarwal – IBM
M. Zhang – Intel
Special Session 5B: SPECIAL SESSION
APPRENTICE – VTS EDITION
Organizer/Moderator: K. S. Kim – Intel
Description: The main objective of this active "panel" is to increase technical interaction among attendees. Team leaders listed below will recruit participants to their team. Each team will try to clearly articulate the problems and come up with proposals to solve this problem. These teams will present their findings and business proposals in front of judges later during the conference. The winning team will be announced during the social event.
A. Crouch – Verigy
J. Dastidar – Altera
A. Gattiker – IBM
R. Kapur – Synopsys
S. Ozev – Duke Univ.
Special Session 5C: SPECIAL SESSION
Organizer: J. Plusquellic – UMBC
April 29th, 2008
|8:30 am - 9:30
Session 6A: TESTING OF ANALOG CIRCUITS
Moderator: J. M. Cooper – Intel
6A.1 A Time-Domain Method for Pseudo-Spectral Characterization
A. Mishra, M. Soma – Univ. of
6A.2 A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays
C. W. Lin, J. L.
Huang – National Taiwan Univ.
6A.3 Fast Accurate Tests for Multi-Carrier Transceiver Specifications: Phase Noise and EVM
Senguttuvan, A. Chatterjee, S. Bhattacharya – Georgia Inst. of Tech.
Session 6B: ATPG I
Moderator: L. Miclea – U Tech of Cluj
6B.1 Automatic Test Pattern Generation for Interconnect Open Defects
S. Spinner, I. Polian,
P. Engelke, B. Becker – Albert Ludwigs Univ.
of Freiburg, M. Keim, W. T. Cheng – Mentor
6B.2 On the Relaxation of N-detect Test Sets
Neophytou, M. Michael – Univ. of Cyprus
6B.3 Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
S. Bahukudumbi, K.
Chakrabarty – Duke Univ.
IP Session 6C: POST-SILICON VALIDATION:
CURRENT PRACTICES AND NEW
Organizer: S. Gupta – Univ. of South. Cal.
Moderator: M. Hunt – Qualcomm
Description: In most existing flows for custom or semi-custom design, the quality of chips shipped to customers is ensured via a sequence of three processes, namely pre-silicon verification of a chip’s design, post-silicon validation of the first-silicon for the design (i.e., the first set of chips fabricated for the design), and testing of each fabricated copy when the design is fabricated in high volume. While verification and testing have been active areas of research, post-silicon validation has developed primarily via intensive engineering practice. However, a noticeable trend has emerged in recent years: Despite advances in design and verification, for high-performance designs it is becoming increasingly common for many causes of circuit misbehavior that can cause significant yield loss to be first discovered during post-silicon validation. This presents numerous challenges, many of interest to the testing community. In this session, validation experts from three leading companies will share their insights. First, they will describe their validation methodologies and some recent case studies. Second, they will present emerging challenges, especially those the testing community may be able to address, e.g., development of new approaches to estimate and enhance quality of validation and new techniques to identify root causes behind erroneous behaviors exposed during validation.
6C.1 Post-silicon validation challenges of highly integrated processors
P. Patra, C. Prudvi – Intel
6C.2 A bug's life... and how the test research community can shorten it
I. Parulkar – Sun
6C.3 Optimizing ATPG scan stimulus for post-silicon validation debug with diagnostic equipment
J. West, J. Drummond, C. Bullock, C. Pilch – Texas Instruments
am - 10:50 am
Session 7A: TESTING OF RF CIRCUITS
Moderator: M. Sawan – Ecole Poly de Montreal
7A.1 Low Cost RF Receiver Parameter Measurement with On-chip Amplitude Detectors
C. Zhang, R. Gharpurey, J. Abraham – Univ. of
Texas at Austin
7A.2 An Integrated BiST Solution for Characterizing RF Transceivers through a Single Measurement
E. Erdogan, S. Ozev – Duke Univ.
7A.3 ACT: Adaptive calibration test based performance improvement and test enhancement of wireless RF front ends
V. Natarajan, R. Senguttuvan, S. Sen, A.
Chatterjee – Georgia Inst. of Tech.
Session 7B: TESTING OF TRANSITION
FAULTS AND SMALL DELAY DEFECTS
Moderator: N. Touba – Univ. of Texas at Austin
7B.1 Synthesis for Broadside Testability of Transition Faults
I. Pomeranz – Purdue Univ, S. Reddy – Univ. of Iowa
7B.2 LSTDF: Low-Switching Transition Delay Fault Pattern Generation
M. Tehranipoor, J. Lee – Univ. of Connecticut
7B.3 Test-Pattern Grading and Pattern Selection for Small-Delay Defects
M. Yilmaz, K. Chakrabarty, – Duke Univ., M. Tehranipoor – Univ. of
IP Session 7C: DESIGN FOR YIELD AND
Organizer: S. Shoukourian – Virage Logic
Moderator: S. Taneja – Cadence
Description: Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for yield optimization. SoC manufacturability and yield entails design-specific optimization of the manufacturing, and thus enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools have been proposed in recent years. Some of these tools are leveraged during back-end design, others are applied post-GDSII, and still others are applied post-design, from reticle enhancement and lithography through wafer sort, packaging, final test and failure analysis. DFY and DFM can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFY and DFM solutions is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads, versus quantified benefits. This session analyzes the key trend and challenges, and provides a set of innovative DFM and DFY practices used for today’s SoC designs.
7C.1 Performance Binning in the Presence of Process Variability
A. Majumdar, V. Ganti - AMD
7C.2 Yield Acceleration based on Design for Yield and Manufacturability
Y. Zorian - Virage Logic
7C.3 A Realistic View of DFM or Search for the Holy Grail
M. d’Abreu - SanDisk
am - 12:10 pm
Session 8A: DELAY TEST AND
Moderator: V. Agrawal – Auburn Univ.
8A.1 Dynamic Compaction for High Quality Delay Test
Z. Wang, D. Walker – Texas A&M Univ.
8A.2 An All-Digital High-Precision Built-In Delay Time Measurement Circuit
M. C. Tsai, C. H. Cheng – Feng-Chia Univ.
8A.3 Error Sequence Analysis
J. Lee, I. Park – Stanford Univ., E. McCluskey - Stanford CRC
Session 8B: TESTING AND ERROR
TOLERANCE FOR EMERGENT
Moderator: R. Makki – UAE Univ.
8B.1 QBIST: 1-Testable Quantum Built-In Self-Test for any Boolean Circuit
Y. H. Chou, I-M. Tsai, S. Y.
Kuo – National Taiwan Univ.
8B.2 A Statistical Approach to Characterizing and Testing Functionalized Nanowires
E. Stern, M. Reed, Y. Makris – Yale Univ., H.
Stratigopoulos – TIMA
8B.3 A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-assemblies
M. Hashempour, Z. M. Arani, F. Lombardi – Northeastern Univ.
IP Session 8C: STIL UTILIZATION IN PRACTICE
Organizer: K. Hatayama – STARC
Moderator: P. Mantri – Sun Microsystems
Description: Standardization of test-related information, not only test data but also testing environmental information, is key for realizing totally standardized test environment from design to diagnosis. On this point, STIL, Standard Test Interface Language (IEEE 1450.x series, see table below) can have an important role.
8C.1 Building Standard Test Environment based on STIL
H. Kamitokusari, T. Aikyo - STARC
8C.2 A STIL-based Desktop ATPG Diagnostic Environment
G.Danialy, S.Pateras– LogicVision
8C.3 STILAccess: Shared Libraries for STIL Parser
H. Date – System JD
pm - 3:15 pm
Special Session 9A: HOT TOPIC SESSION
YIELD MANAGEMENT & DPPM REDUCTION
P. Ehlig, A. Kokrady – Texas Instruments
Moderator: T. M. Mak – Intel
Description: With shrinking technology, it is getting harder to manufacture and test memories which today occupy more than 50%-60% of chip area and dominate the defects and customer returns in today’s integrated circuits. Previously unheard of fault/defect types are causing designs to fail reducing yield and increasing Defective Parts per Million (DPPM). It is important for the design & test community to understand the need to screen and analyze the defects and find out techniques to mitigate them. In this session, we explore various ways of reducing the impact on yield and DPPM.
9A.1 Memory Yield Improvement through Multiple Test Sequences and Application-aware Fault Models
A. Kokrady, C.P. Ravikumar, N.
Chandrachoodan – Texas Instruments
9A.2 Lithography and Memories: >From Shapes to Electrical
P. Gupta – Univ. of Cal. Los Angeles,
C. Wu – Aprio Technologies
9A.3 Panel Discussion: Yield Management and DPPM Reduction for sub micron memories
P. Ehlig – Texas Instruments
Y. Zorian – Virage Logic
R. Aitken – ARM
Session 9B: SPECIAL SESSION
NANOELECTRONICS – WHAT NEXT? FROM
MOORE’S LAW TO FEYNMAN’S VISION
S. Mourad – Santa Clara Univ.,
Y. Zorian – Virage Logic
Moderator: S. Mourad – Santa Clara Univ.
Description: The limit of present silicon transistors is set by the manufacturing process and not by the laws of physics. Emerging nanomaterials has provided new possibilities for higher packing density, higher carrier mobilities, and higher/lower dielectric constants. Although nanotechnology is usually defined as utilizing technology with less than 100nm in the minimum feature size, nanoelectronics often refer to devices that are so small that inter-atomic interaction, ballistic transport, and quantum mechanical properties need to be studied. These phenomena are expected to assume much more prominent roles in silicon-based devices fabricated using sub-45 nm technologies.
Nanoelectronic devices such as Single Electron Transistor, Resonant Tunnel Diodes and Quantum Dot Arrays are still under development as practical circuitry, but they do hold a great promise. This is also true of molecular devices that can self-assemble to form a large system. One of the best known families of nanomaterials is carbon nanostructures such as nanotube, nanofiber, and graphene. They hold great promise as candidates for ultra-fast switches as well as interconnect and thermal interface materials. In this session, three speakers will present different facets of nanoelectronics to prepare us test engineers for the challenges integrated circuit technology faces now and in the near future.
9B.1 One Dimensional Nanostructures and their Applications
M. Meyyappan – NASA Ames
9B.2 Emerging Nanoelectronic Devices
B. Yu– UARC/NASA Ames Research Center
9B.3 Carbon Nanostructures as On-chip Interconnects
C. Y. Yang - Santa Clara Univ.
Session 9C: HOT TOPIC SESSION
TTTC 2008 BEST DOCTORAL THESIS
Organizer: Y. Makris – Yale University
Moderator: H. Stratigopoulos – TIMA
M. Abadir – Freescale
T. M. Mak – Intel
T. McLaurin – ARM
J. Rajski – Mentor Graphic
J. Saxena – Texas Instruments
Description: This session is the final round of the TTTC 2008 Best Doctoral Thesis Contest. This contest is organized by the TTTC Student Activities Committee for the fourth consecutive year and aims to promote and strengthen the interaction between graduate students and the industrial community, as well as to serve as a process by which student work is exposed to and tested under real-life industrial needs. This is achieved by offering students the chance to present their work in a conference environment to academic and industrial test experts, who will evaluate and comment in terms of novelty and advancement of industrial practice.
In the preliminary round of this contest, doctoral students who are expected to graduate in 2008 were invited to submit a one page abstract of their thesis, where they defined the problem and its relevance to industry, described existing industrial practices for solving the problem and explained the proposed methodology and how it advances the theory and/or practice in the particular field. The abstracts were reviewed by a panel of industrial and academic experts and a set of finalists were selected for the final round of the contest.
In this final round, during a dedicated session at the IEEE VLSI Test Symposium (VTS’08), each contestant is given a ten minute slot in front of a panel of experts, split equally between oral presentation and Q&A period. The panel of experts will judge the presented doctoral theses with regards to theoretical advancement, industrial relevance and presentation, and the winner of the contest will receive the 2008 TTTC Doctoral Thesis Award during the social event of the Symposium, to which all finalists are invited. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.
Sudarshan Bahukudumbi (Duke University - USA), Giuseppe Di Guglielmo (Universita di Verona - Italy), Francois-Fabien Ferhani (Stanford University - USA), Michelangelo Grosso (Politecnico di Torino - Italy), Gurgen Harutyunyan (Yerevan State University - Armenia), Naghmeh Karimi (University of Tehran - Iran), Ritesh Turakhia (Portland State University - USA), Devanathan Varadarajan (Indian Institute of Technology Madras, India)
|3:30 pm - 11:00 pm
Wednesday, April 30th, 2008
|9:00 am - 10:30 am
Session 10A: TESTING OF MIXED SIGNAL
Moderator: I. Hartanto – Xilinx
10A.1 Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits
B. Kim, J.
Abraham – Univ. of Texas at Austin, N. Khouzam – National Semiconductor
10A.2 Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
S. Biswas, R. S. Blanton – Carnegie Mellon Univ.
10A.3 Parallel Loopback Test of Mixed-Signal Circuits
J. Park, H. Shin, J. Abraham – Univ. of Texas at
Session 10B: ATPG II
Moderator: H. Konuk – Broadcom
10B.1 Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests
I. Pomeranz – Purdue Univ., S. Reddy – Univ. of Iowa
10B.2 An ATPG Methodology to Detect Weight Related Defects in Threshold Logic Gates
Goparaju, S. Tragoudas – Southern Illinois Univ.
10B.3 Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
S. Rajamani – Qualcomm, M. Bushnell – Rutgers Univ., V. Agrawal – Auburn Univ.
IP Session 10C: TESTING FOR COMPLEX
FAILURE MECHANISMS AND PROCESS
VARIATIONS OF MEMORIES
Organizers: M. Azimane – NXP
Moderator: B. Wang – AMD
Description: Memory area on current designs in the 90nm, 65nm and 45nm designs is increasing exponentially given the nature of applications and the drive to embed entire systems on a single chip. With ever increasing process complexity and shrinking technologies, different defect types that manifest themselves as complex failure mechanisms and process variations on memories are also increasing proportionally. Traditional memory test techniques like functional vectors are no longer sufficient. In the mean time, new DFT methods and Built-in Self-Test (BIST) approaches are evolving to test for these defects and garner enough data to increase memory test efficiency.
In the first presentation, Azimane et al. from NXP Semiconductors will focus on additional DFTs that could be implemented in addition to BIST test algorithms to catch complex failure mechanisms and worst case process variations. They show that the fault coverage of conventional march tests have reached saturation phase and time has come to jump to new test methods.
In the second presentation, and in cooperation between LIRMM and Infineon, Dilillo et al. have analyzed the impact of technology scaling on defects and parameter deviations in embedded SRAMs. They showed how the impact of manufacturing defects may vary with the level of integration (130 nm down to 45 nm) of eSRAMs core-cell belonging to the same family. Secondly, they illustrate the effects of technology scaling (130 nm down to 45 nm) on device parameter variations.
In the third presentation, Jayaram et al. from Texas Instrument will address the pros/cons of BIST techniques and show how programmable BIST offers almost unlimited flexibility on screening known and unknown defects in the presence of process variation. In addition, they will offer some case-studies on hard-to-screen defects and present some implementation-level details of programmable BIST on today’s complex designs. They will also address the aspect of designing memories to make test easier and highlight some features that are critical in enabling efficient debug. Finally, they will cover some aspects of hard vs. soft repair and external vs. Built-in Self-Repair (BISR).
10C.1 Dealing with complex failure mechanisms for high quality testing in Embedded SRAMs
Azimane, B.Kruseman, S. Eichenberger – NXP
10C.2 Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs
L. Dilillo, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel – LIRMM, M.
Bastian, V. Gouin – Infineon
10C.3 Flexible Memory Test Architectures for
Combating Subtle Defects and Process
V. Jayaram, S. Lai – Texas
|10:20 am - 11:20 am
Session 11A: DEBUG AND DIAGNOSIS
Moderator: M. Michael – Univ. of Cyprus
11A.1 Fast Measurement of the "Non-deterministic Zone" in Microprocessor Debug using Maximum Likelihood Estimation
D. Tadesse, R. I. Bahar – Brown Univ., J.
Grodstein – Intel
11A.2 Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
J. S. Yang, N. Touba – Univ. of Texas at
11A.3 A General Failure Candidate Ranking Framework
C.C. Yen, S.T. Lin, H. Lin –
Springsoft, K. Yang, Y. C. Hsu, T. Liu – Novas
Special Session 11B: SPECIAL SESSION
A SURVEY OF ON-CHIP DELAY
MEASUREMENT TECHNIQUES FOR
PRODUCTION TEST – FROM NANO TO
Organizer & Presenter: S. Sunter – LogicVision
Abstract: As CMOS IC dimensions scale below 90 nm, delays-of-interest range from nanoseconds to picoseconds. This increases the need for greater time measurement accuracy but off-chip (ATE-based) delay measurement techniques are becoming severely limited by fundamental properties of signal access paths off-chip and on-chip, such as noise, wire length, and impedance variation. On-chip measurement techniques have been proposed by IC designers, DFT engineers, and test engineers, with claimed accuracies ranging from nanoseconds to femtoseconds, at least in simulation.
This tutorial will survey most of the papers that provide silicon results published in the last 10 years, in both design and test journals/conferences, and some representative papers that include only simulated results, to discover the most promising directions for measuring and production testing today’s and future delays-of-interest. Delay parameters include instantaneous delay, average delay, and delay variation (long and short term, including jitter) in digital, analog, and wire paths, and they typically depend on voltage, frequency, and conditions. The measurement techniques will be categorized by suitability for measurement of one-shot and periodic events, then by measurement principle, and lastly by circuit technique and reported real-silicon capabilities.
The goal is to identify principles and techniques suitable for production testing (quick and process tolerant, using insignificant silicon area) and for IC characterization and debug too (flexible to handle unanticipated delays and accuracy).
Some of the conclusions are: isolation between engineers in different disciplines (design, DFT, test) results in sub-optimal solutions; simulations can be enhanced to include many deleterious effect but real silicon provides surprises when it comes to picoseconds; progress in the last 10 years has not tracked technology scaling because of discipline isolation and emphasis on simulation; a new standard test pin type might accelerate progress towards meeting production test requirements.
The intended audience is DFT and test engineers, and researchers.
IP Session 11C: NEW EMERGING PRACTICES
FOR SEMICONDUCTOR TEST
Organizers: P. Roddy – Advantest
Moderator: D. Appello – ST Microelectronics
Description: This session will focus on practical applications for the semiconductor test process. The rapidly expanding development of new semiconductor products is putting a strain on the industry's test resources. Several of the ITC 2007 speakers highlighted the additional effort that will be required in the test area, to keep up with all the new designs. This session will explore new and innovative test applications that are being used to address these challenges.
11C.1 Development of Common Tools & Tester Language for ATE
P. Decher – TSSI
11C.2 New RF Testing Innovations
K. Schaub – Advantest
11C.3 Migration of PXI Instruments into Semiconductor Production Test
E. Starkloff – National
|11:40 am - 12:40 pm
Session 12A: FAULT TOLERANCE
Moderator: F. Lombardi – Northeastern Univ.
12A.1 Algorithm Level Fault Tolerance: a New Technique to Cope with Radiation Induced Faults in Matrix Multiplication Algorithms
Lisboa, L. Carro – Universidade Federal do
Rio Grande do Sul, C. Argyrides, D. Pradhan – Bristol Univ.
12A.2 Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects
Zhang, H. Li, X. Li, Y. Hu – Chinese Academy of
12A.3 Low Cost Highly Robust Hardened Storage Cells Using Blocking Feedback Transistors
Nicolaidis – TIMA, D. Alexandrescu, R. Perez – IRoC
Session 12B: TESTING OF PATH DELAY
Moderator: C. Aktouf – Defacto
12B.1 Multiple Coupling Effects Oriented Path Delay Test Generation
M. Zhang, H. Li, X. Li – Chinese Academy of Sciences
12B.2 A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
P. Bernardi, E. Sanchez, M. Sonza Reorda – Politecnico di Torino, K. Christou, M. Michael – Univ. of Cyprus
12B.3 An Industrial Case Study of Sticky Path-Delay Faults
I. Huang, S. Gupta – Univ. of South. Cal.,
Y. S. Chang – Intel, S. Chakravarty – LSI Logic
IP Session 12C: FAULT LOCALIZATION PRACTICES
Organizer: S. Tammali – Texas Instruments
Moderator: B. Eklow – Cisco
12C.1 Current practices of FA Engineer / DFT engineer and Challenges
S. Tammali, K. Scott Wills, D.
Paul – Texas Instruments
12C.2 Principle and Practice of Modern Scan Diagnostics
S. Cook, B. Benware – Mentor
12C.3 Tester-based Scanning Optical Microscope Techniques for Fault Localization
J. C. Phang – SEMICAPS, M. R. Bruce – AMD
|2:00 pm - 3:30 pm
Special 13A: SPECIAL SESSION
MITIGATING RELIABILITY, YIELD AND
POWER ISSUES IN NANO-CMOS: DESIGN
PROBLEM OR EDA PROBLEM?
Organizer: M. Nicolaidis – TIMA
Moderator: Y. Zorian – Virage Logic
Co-Organized with: IEEE Design & Test of Computers
Description: Silicon based CMOS technologies are fast approaching their manufacturability limits. In newer processes, power dissipation, fabrication yield, and reliability are steadily worsening, making further nanometric scaling increasingly difficult. In particular, yield as well as reliability are threatened by issues such as manufacturing process variations, on-chip voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk.
S. Bhabhu – Cadence
R. A. Parekhji – Texas Instruments
M. Nicolaidis – TIMA
M. Zhang – Intel
Session 13B: HOT TOPIC SESSION
BIOMEDICAL DEVICES – NEW TEST
Organizer: B. Kaminska – Simon Fraser Univ.
Moderator: K. Eshraghian– Univ. of Cal., Merced
13B.1 Massively parallel wireless sensing from the cortex: Design and test challenges
M. Sawan– Ecole Polytechnique
13B.2 Design and Calibration of EEG Electrode Arrays for Wearable BCI
G. Cauwenberghs – Univ. of
Cal., San Diego
13B.3 Testing of Digital Microfluidic Biochips: Fault Models, Test and Fault Diagnosis
Chakrabarty – Duke Univ.
Session 13C: SPECIAL SESSION
IS UBIQUITOUS RF AT ODDS WITH TEST?
Organizers: A. Khoche – Verigy
Moderator: A. Chatterjee – Georgia Inst. of Tech.
Description: The drive for using RF to provide universal connectivity is forcing various wireless standards being supported in a single device. Moreover this functionality is expected in consumer devices where the cost pressure is significant. The cost pressure coupled with the everlasting quest for miniaturization leads to many of these wireless interfaces being added to a single chip or a package. The instrumentation required for testing an RF interface is traditionally more expensive than the digital, memory or mixed signal components. The proliferation of RF interfaces on a chip/package would push the test cost even higher and could potentially become a bottleneck in enabling such ubiquitous RF devices. This panel will discuss state of RF test technology with respect to the needs of such ubiquitous RF devices to identify the gaps, if any.
O. Martinez – Qualcomm
G. McCarter – Verigy
K. Harvey – Teradyne
K. Schaub – Advantest
P. Berndt – Cypress Semiconductor
M. Berry - Amkor