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IEEE International Workshop
Current & Defect Based Testing
Held in Conjunction with International Test Conference Test Week (ITC 2007)
Submission Deadline Extended September 1st, 2007!
CALL FOR PAPERS & PARTICIPATION
As we push deeper into nanometer technologies, systematic defects are outstretching random defects as the dominant yield limiter and are presenting unique challenges to the yield enhancement community. New methodologies are required to detect, monitor, and resolve systematic defect mechanisms at the 90nm technology node and below. As mainstream silicon manufacturing processes scale to and beyond the 65-nm node, we also find the mean and variance of process variations increasing. Fallout caused by systematic defects is obfuscated by process variations, making them more difficult to distinguish using traditional testing methods. This year's workshop is charged with determining whether defect-based test is better positioned to provide information regarding root cause, and whether such methods can help with the identification and isolation of systematic defects.
The IEEE International Workshop on Current and Defect Based Testing (DBT 2007) is aimed at addressing these issues and others related to this year’s theme “Process Variations + Systematic Defects: Can DBT Help?” Paper presentations on topics related to the workshop’s theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.
The workshop includes (but is not limited to) the following topics:
To present at the workshop, submit a postscript or Acrobat (PDF) version of an extended abstract of at least 1000 words via E-mail to the Program Chair by September 1, 2007. Each submission should include full name and address of each author, affiliation, telephone number, FAX and E-mail address. The presenter should also be identified. Camera-ready papers for inclusion in the digest of papers will be due on Oct. 6, 2007. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.
Technical Program Submission:
Vice General Chair
For more information, visit us on the web at: http://dbt.tttc-events.org/
IEEE International Workshop On Current & Defect Based Testing is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 2ND VICE CHAIR
DESIGN & TEST MAGAZINE
& SOUTH PACIFIC
1ST VICE CHAIR
EAST & AFRICA
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