TTTC's Electronic Broadcasting Service
International Test Synthesis Workshop (ITSW 2007)
CALL FOR PARTICIPATION
Theme: Testing a Design in its Natural Habitat
Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.
As ITSW moves to its new habitat in San Antonio, Texas, this year’s workshop will focus on post-silicon chip quality. ITSW 2007 will look at all aspects of testing in its natural habitat such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No-Fault Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will also consider the usual papers in the area of Test Synthesis including, but not limited, to the following:
For more information, please refer to the web site: http://www.tttc-itsw.org.
Past General Chair
Local Arrangements Chair
For more information, visit us on the web at: http://www.tttc-itsw.org
The 14th International Test Synthesis Workshop (ITSW 2007) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 2ND VICE CHAIR
DESIGN & TEST MAGAZINE
& SOUTH PACIFIC
1ST VICE CHAIR
EAST & AFRICA
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