VTS 2006 - Call for Participation

CALL FOR PARTICIPATION

- LAST CHANCE TO TAKE ADVANTAGE OF DISCOUNTED VTS 2006 ROOM RATES -
Room Rates At the Claremont Resort Will Increase After APRIL 7, 2006

- ADVANCE REGISTRATION DEADLINE EXTENDED UNTIL APRIL 17, 2006 -

Program Highlights -- More Information -- Committees

Program Highlights

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world's leading test experts and professionals from both industry and academia join to present and debate key issues in testing. VTS 2006 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Embedded Tutorials, Panels, Hot Topic Sessions, Full-day Tutorials, co-located Workshops, and the Innovative Practices Track.

TECHNICAL PAPER SESSIONS will present the latest research results in test. VTS 2006 technical paper sessions include:

Delay Testing
High-speed Interconnect Test
Heat & Power Issues in Test
Test Quality
IP Protection
Flash & Memory Testing
Yield Analysis
Test Generation and Test Flows
MEMS Testing
Wireless Testing
Nanoscale Testing
Test Size Reduction
Transistor Level & Scan-based Diagnosis
RF, Analog & Mixed-Signal Test
Designing Robust CMOS and Nanoelectronics

KEYNOTES

Keynote Address: "Finding The Path To 100 Billion Transistor Devices", Mike Mayberry, Vice President of Technology and Manufacturing Group, Intel Corp.
Invited Keynote: "Nanoscale Challenges in Device Test and Diagnostics", Vahe Sarkissian, Chairman, President and CEO, FEI Company

INNOVATIVE PRACTICES (IP) TRACK highlights cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them, including:

Reliability Screening Methods
Scan Compression
Nanometer IC Testing - Perspectives from Foundries
TRP in Action
Test Strategies of Leading Edge SoCs
High Test Parallelism: Throughput and Quality at a Low Cost
Soft Error Impact on Modern Systems
System-in-Package Design and Test Practices
Impact of Variations on Design and Test
Making the (Yield) Difference: DFY/DFM

SPECIAL SESSIONS will include:

EMBEDDED TUTORIALS: Functional ATPG; Silicon Debug Challenges for Nanometer Designs
HOT TOPIC SESSION on Signal Integrity
NEW TOPIC: Emerging Nanoelectronic Devices for High Speed, Low power applications
PANELS: Real-Time Volume Diagnostics: Requirements and Challenges; Three Questions to Oracle; Changing Role of Test: Is ATE Ready?
ELEVATOR TALK SESSION will provide a forum for participants to present 5-min talks.

FULL-DAY TUTORIALS and WORKSHOPS complement the core technical program of VTS.

WORKSHOPS:
Open Source Test Technology Tools Workshop
Wireless Test Workshop
Infrastructure IP Workshop

TUTORIALS:
What’s going on inside? From Basic to Advanced Techniques for Silicon Debug and Defect Diagnosis
Delay Testing: Theory and Practice
Testing Circuit Marginalities

The social program at VTS provides an opportunity for informal technical discussions among participants. Berkeley, California, provides a very attractive backdrop for all VTS 2006 activities. We are sure that you will find VTS 2006 enlightening, thought-provoking, rewarding, and enjoyable!

More Information

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For more information on the VTS 2006 Test Event, visit the VTS website at

http://www.tttc-vts.org

or contact:

GENERAL CHAIR
Irith Pomeranz
Purdue University
West Lafayette, IN, USA
T: +1-765-494-3357
E: pomeranz@ecn.purdue.edu

PROGRAM CHAIR
Paolo Prinetto
Politecnico di Torino
Torino, Italy
T: +39-011-564-7007
E: Paolo.Prinetto@polito.it

Committees

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General Chair
I. Pomeranz - Purdue U

Program Chair
P. Prinetto - Poli di Torino

Vice-General Co-Chairs
S. M. Reddy - U Iowa
H.-J. Wunderlich - U Stuttgart

Vice-Program Co-Chairs
A. Orailoglu - UC San Diego
J. Segura - U Illes Balears

New Topics
B. Courtois - TIMA

Special Sessions
P. Maxwell - Agilent
C. Metra - U Bologna

Innovative Practices Track
S. Mitra - Intel

Publications
S. Ravi - NEC

Publicity
A. Raghunathan - NEC

Audio/Visual
D. Gizopoulos - U Piraeus

Finance
M. Renovell - LIRMM

Local Arrangements
B. West - Credence

Past Chair
S. Dey - Ortiva Networks

Ex-Officio
Y. Zorian - Virage Logic

Program Committee:
M. Abadir - FreeScale
J. A. Abraham - UT Austin
V. D. Agrawal - Auburn U
L. Anghel - TIMA
D. Appello - STMicroelectronics
B. Becker - U Freiburg
A. Benso - Poli di Torino
C.-H. Chiang - Lucent
C.J. Clark - Intellitech
D. Conti - IBM
B. Cory - nVidia
R. Galivanche - Intel
P. Girard - LIRMM
S. Gupta - USC
I. Harris - UC Irvine
K. Hatayama -Renesas
S. Hellebrand - U Paderborn
S. Kajihara - Kyushu Inst Tech
B. Kaminska - Pultronics
R. Kapur - Synopsys
A. Koche - Agilent
H. Konuk - Broadcom
C. Landrault - LIRMM
R. Makki - UAE U
H. Manhaeve - QStar
E.J. McCluskey - Stanford U
S. Mourad - Santa Clara U
P. Muhmenthaler - Infineon
J. Plusquellic - U Maryland
J. Rajski - Mentor Graphics
G. Roberts - McGill U
R. Segers - Philips
M. Soma - U Washington
S. Sunter - LogicVision
S. Tabatabaei - Virage Logic
C. Thibeault - E Tech Sup Montreal
J. Tyszer - Poznan U Technology
R. Ubar - U Tallinn
C. -W. Wu - Nat Tsing Hua U
A. Yessayan - Virage Logic

Steering Committee:
J. Figueras - U Poli Catalunya
A. Ivanov - UBC
M. Nicolaidis - iRoC
R. Roy - Zenesys
A. Singh - Auburn U
P. Varma - Blue Pearl
Y. Zorian - Virage Logic

For more information, visit us on the web at: http://www.tttc-vts.org

The 24th IEEE VLSI TEST SYMPOSIUM (VTS 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	24th IEEE VLSI TEST SYMPOSIUM (VTS 2006) April 30th - May 4th, 2006 Claremont Resort, Berkeley, California, USA http://www.tttc-vts.org