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11th IEEE European Test Symposium (ETS'06)
May 21-25, 2006
Hilton Hotel, Southampton, United Kingdom


- Discount Registration Available Till April 21, 2006! -

Overview -- Technical Program -- Committees


The IEEE European Test Symposium (ETS) is Europe's premier forum dedicated to presenting and discussing scientific results, emerging ideas, practical applications, hot topics, and new trends in the area of electronic-based circuit and system testing. In 2006, ETS will take place in Southampton, the historic port on the south coast of England. ETS'06 is being organized by the University of Southampton and sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.


The ETS'06 program offers the following items.

  • A plenary opening session, with a keynote address by ARM Chairman Sir Robin Saxby and an invited address by Manchester's Prof.Dr. Steve Furber.
  • Paper presentations in three parallel tracks.
  • Three parallel panel sessions on hot (test) topics.
  • Poster sessions.
  • NEW: Vendor Sessions with technical marketing presentations.
  • NEW: Student Forum with posters and a dedicated panel session.
  • Plenty of networking opportunities, especially during the Social Event.


ETS'06 offers two full-day TTEP tutorials on Sunday May 21, 2006.

  • DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield
    Presenters: Srikanth Venkataraman (Intel, US) and Nagesh Tamarapalli (Mentor Graphics, US)
  • Delay-Fault Testing: From Basics to ASICs
    Presenters: Ben Bennetts (Bennetts Associates, UK) and Bram Kruseman (Philips Research, NL)


ETS'06 offers a Social Event in the historic maritime surroundings of Southampton. The friendly, inspiring atmosphere of ETS'06 allows plenty of opportunities to meet, network, and interact with your colleagues in an informal setting.


You are cordially invited to participate in ETS'06. Discount registration is available until April 21, 2006 on-line via Registration includes access to all sessions, Formal Proceedings, Informal
Digest of Papers, post-symposium CD-ROM by mail, luncheons, and dinners; for more information, check the ETS'06 web site.

Technical Program

SUNDAY MAY 21, 2006
08:30-10:00 Session 1: Plenary Opening
Moderator: H.-J. Wunderlich (Univ. Stuttgart, DE) - ETS'06 Vice Program Chair

Welcome Address
B.M. Al-Hashimi (Univ. of Southampton, UK) - ETS'06 General Chair

Keynote: Innovation and Wealth Creation from Technology
R. Saxby (ARM, UK)

Presentation of ETS'05 Best Paper Award
M. Renovell (LIRMM, FR) - ETS'05 Program Chair

Invited Address: Living with Failure: Lessons From Nature?
S. Furber (Univ. of Manchester, UK)

Introduction to ETS'06 Technical Program
E.J. Marinissen (Philips Research, NL) - ETS'06 Program Chair

Practical Aspects of ETS'06
M. Zwolinski (Univ. of Southampton, UK) - ETS'06 Local Arrangements Chair

10:00-11:00 Session 2: Posters and Coffee/Tea Break

Input Cones Based on Test Sequences for Synchronous Sequential Circuits
I. Pomeranz (Purdue Univ., US), S. Reddy (Univ. of Iowa, US)

Strengthening Logic BIST with IDDQ - Taking the Best of Both Worlds
J.S. Vaccaro, T. Colunga, L. Benecke, S. Mahadevan (Freescale Semiconductor, US), H. Manhaeve (Q-Star Test, BE)

Extended Compatibilities for Scan Tree Construction
Z. You, M. Inoue, H. Fujiwara (Nara Inst. of Science and Tech., JP)

Proposal of a Clock Signal Generation/Detection Method for Crosstalk Aware Design
Y. Miura (Tokyo Metropolitan Univ., JP)

Efficient and Accurate Analog Sinewave Generator for BIST Applications
M.J. Barragán, D. Vazquez, A. Rueda, G. Huertas, J.L. Huertas Diaz (Univ. de Sevilla, ES)

Some Improvements of Phase-Spectrum ADC Hysteresis Test for Practical Application
D. Slepicka, D. Dallet (Laboratoire IXL, FR), V. Shitikov, F. Barbara (Schlumberger, FR)

Bitline-Coupled Precharge Faults and Their Detection in Memory Devices
Z. Al-Ars, S. Hamdioui (Delft Univ. of Tech., NL), G. Müller, J. Vollrath (Infineon Technologies, DE)

Automatic Test Program Generation Tool for Mixed-Signal Device Interface Boards
B. Kim (Univ. of Alabama, US), V. Kalyanaraman, P. Variyam (Texas Instruments, US), S. Cherubal (WiQuest Communications, US)

11:00-12:30 Session 3A: Delay Fault Testing
Moderators: W. Anheier (Bremen Univ., DE) and A. Majhi (Philips Research, NL)

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable Signals
G. Xu, A. Singh (Auburn Univ., US)

Dynamic Voltage Scaling Aware Delay Fault Testing
N.B. Zain Ali, M. Zwolinski, B.M. Al-Hashimi (Univ. of Southampton, UK), P. Harrod (ARM, UK)

Enhancing Delay Fault Coverage through Low Power Segmented Scan
S. Reddy, Z. Zhang (Univ. of Iowa, US), J. Rajski (Mentor Graphics, US), B.M. Al-Hashimi (Univ. of Southampton, UK)

11:00-12:30 Session 3B: Single-Event Upsets
Moderators: B. Becker (Univ. Freiburg, DE) and M. Sachdev (Univ. of Waterloo, CAN)

Single-Event Upset Analysis and Protection in High Speed Circuits
M. Hosseinabady, P. Lotfi-Kamran (Univ. of Tehran, IR), G. Di Natale, S. Di Carlo, A. Benso, P. Prinetto (Politecnico di Torino, IT)

Soft Error Resilient Linear DSM Systems: Probabilistic Error Correction vs. State Restoration
M. Ashouei, S. Bhattacharya, A. Chatterjee (Georgia Inst. of Tech., US)

Avoiding Circuit Simulation for the Analysis of Single Event Transient Propagation in Combinational Circuits
C. Neves (Univ. Federal de Pelotas, BR), I. Ribeiro, E. Henes, G. Wirth (UERGS, BR), F. Lima Kastensmidt (UFRGS, BR), J.L. Güntzel (UFPEL, BR)

11:00-12:30 Vendor Session 3C: Getting More Out of Test
Moderators: G. Francis (Philips Semiconductors, UK) and H. Lang (Freescale Semiconductor, DE)

Test Management Systems - A New Category in the Testing Arena
D. Glotter (OptimalTest, Israel)

The Growing Impact of Manufacturing Test - Enabling DPM Reduction and Yield Learning
J. Rajski, B. Watt (Mentor Graphics, US)

Visibility Enhancement for Silicon Debug
Y.-C. Hsu, R. Ruiz (Novas Software, US)

12:30-14:00: Lunch
14:00-15:30 Session 4A: Memory Testing - 1
Moderators: J. Rivoir (Agilent Technologies, DE) and C. Hill (Mentor Graphics, UK)

Minimal March Tests for Dynamic Faults in Random Access Memories
G. Harutunyan, V. Vardanian (Virage Logic, Armenia), Y. Zorian (Virage Logic, US)

A 22n March Test for Realistic Static Linked Faults in SRAMs
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto (Politecnico di Torino, IT)

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories
Y.-J. Huang, J.-F. Li (National Central Univ., TW)

14:00-15:30 Session 4B: Test of Reconfigurable Systems
Moderators: E. Larsson (Linköpings Univ., SE) and B. West (Credence Systems, US)

Fault Identification in Reconfigurable Carry Lookahead Adder Implementations Targeting Nanoelectronic Fabrics
W. Rao, A. Orailoglu (UCSD, US), R. Karri (Polytechnic Univ., US)

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
K. Katoh, H. Ito (Chiba Univ., JP)

Fault Injection-based Reliability Evaluation of SoPCs
M. Sonza Reorda, L. Sterpone, M. Violante (Politecnico di Torino, IT), M. Portela-Garcia, C. Lopez-Ongil, L. Entrena (Univ. Carlos III de Madrid, ES)

14:00-15:30 Vendor Session 4C: At-Speed Test and Test Compression
Moderators: M. Lousberg (Philips Research, NL) and K. Thapar (Mentor Graphics, UK)

Consideration of On-Chip Compression Alternatives
R. Illman (Cadence Design Systems, UK), B. Keller (Cadence Design Systems, US)

Keeping Test Simple
R. Kapur (Synopsys, US)

Facilitating At-Speed Test at the Register Transfer Level
S. Swaminathan (Qualcomm, US), R. Marlett (Atrenta, US)

15:30-16:30 Session 5: Student Forum Posters and Coffee/Tea Break

Modeling and Automatic Test Pattern Generation for Mixed-Signal Boards in Maintenance Testing: Dealing With Simple Time Aspects
B. Gilles (Univ. de Bretagne Occidentale, FR)

Accurate IDD Testing of Mixed-Signal Integrated Circuits using Auto-Zero Voltage Comparator
V. Nagy, V. Stopjaková (Slovak Univ. of Tech., Slovakia)

Hardware Implementation of the Backtrace Algorithm
M. Stáva, O. Novák (Czech Tech. Univ., CZ)

Small Delay Defect Detection in the Presence of Process Variations
R. Tayade, S. Sundareswaran, J. Abraham (Univ. of Texas-Austin, US)

Connectionless Testing
M. Salamati, D. Stranneby (Orebro Univ., SE)

STESOC: A Software-Based Test Access Mechanism
M. Tuna, M. Benabdenbi, A. Greiner (Univ. of Paris VI, FR)

An Efficient Online BIST Architecture for NoCs
M. Hosseinabady, M. Nazm Bojnordi, A. Banaiyan, Z. Navabi (Univ. of Tehran, IR)

16:30-17:30 Session 6A: Memory Testing - 2
Moderators: S. Hamdioui (Delft Univ. of Tech., NL) and P. Hughes (ARM, UK)

Retention-Aware Test Scheduling for BISTed Embedded SRAMs
Qiang Xu (Chinese Univ. of Hong Kong, HK), B. Wang (ATI Technologies, CAN), F.Y. Young (Chinese Univ. of Hong Kong, HK)

A Transparent-Based Programmable Memory BIST
S. Boutobza (Synopsys, FR), M. Nicolaidis (TIMA Laboratory, FR)

16:30-17:30 Session 6B: Test and Measurement
Moderators: G. Russell (Univ. of Newcastle-upon-Tyne, UK) and Y. Zorian (Virage Logic, US)

A Flexible and Scalable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare
B. Laquai, M. Hua, G. Schulze, M. Braun (Agilent Technologies, DE)

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
M. Collins, B.M. Al-Hashimi (Univ. of Southampton, UK)

16:30-17:30 Vendor Session 6C: Jitter Test
Moderators: J.-L. Carbonero (STMicroelectronics, FR) and E. Volkerink (Agilent Technologies, US)

Moving Jitter Injection for High-Speed Digital Streams from the Analog Domain to the Digital Domain
R. Whyte (Credence, UK)

High Throughput PLL Testing - A Fast Method to Test Frequency and Jitter on Clock Outputs in Production
M. Braun, M. Fischer, J. Wolf (Agilent Technologies, DE)

17:30-19:00 Panel Session 7A:
Screening Is Only For Those Who Don't Know How To Test Better

Organizers: E.J. Marinissen (Philips Research, NL) and A. Singh (Auburn Univ., US)
Moderator : P. Maxwell (Avago Technologies, US)

Screening is rejecting chips that pass all tests, but are suspect of being test escapes or latent reliability problems. Screening can for example be done on wafer neighborhoods (a die with too many failing dies as neighbors is suspect) or on parametric outlier measurements (a die with measurement values within spec, but sufficiently different from other passing dies). This panel session will discuss screening and its implications. What hardware and software
infrastructure is necessary to enable screening? How effective is screening, and how is that measured? How expensive is screening; aren't we simply throwing away good dies? How does screening relate to burn-in? And, shouldn't we be improving our tests themselves?


* Tom S. Barnett (IBM Microelectronics, US)
* Dan Glotter (OptimalTest, Israel)
* Bob Madge (LSI Logic, US)
* Adit Singh (Auburn University, US)
* Co van Winsum (Philips Semiconductors, NL)

17:30-19:00 Panel Session 7B:
How Relevant is Your Academic Preparation to Your Current Job Function?

Organizers: E. Larsson (Linköpings Univ., SE) and N. Nicolici (McMaster Univ., CAN)
Moderator : M. Sonza Reorda (Politecnico di Torino, IT)

Universities strive to define appealing curricula to attract and educate top students and perform research that will impact long term industry needs. Employers look for skillful employees who can tackle the problems that require immediate solutions and who also have the depth to foresee the challenges of tomorrow. Given both the common interests and cultural differences between academia and industry, the question is how can we further improve the academic preparation to better serve the (test) industry in the long run? Join recent university graduates who will share their experience in transitioning from student to profession.


* Zaid Al-Ars (Delft Univ. of Tech., NL)
* Thomas Clouqueur (AMD, US - ex Univ. of Wisconsin-Madison, US)
* Artur Jutman (Tallinn Univ. of Tech, EST)
* Martin Keim (Mentor Graphics, US - ex Univ. of Freiburg, DE)
* Krishna Chakravadhanula (Cadence, US - ex Univ. of Texas-Austin, US)
* Ross Torkington (ARM, UK - ex Sheffield Univ., UK)
* Erik Volkerink (Agilent Technologies, US - ex Stanford Univ., US)

17:30-19:00 Panel Session 7C:
EDA Test Synthesis, ATE Test Application - The Next Big Challenges?

Organizer: B. Bennetts (Bennetts Associates, UK)
Moderator: R. Marlett (Atrenta, UK)

The EDA vendors have risen to the challenges of improved test-synthesis tools for at-speed test, test-data compression, and repairable memories. The ATE vendors have improved the capabilities of semiconductor testers in terms of measurements on high-speed buses: jitter injection and analysis, bit-error rate assessment, etc. So, what's next? What will be the major challenges of the test-synthesis and test-application vendors over the next five years as we drive down into 65nm technologies? More of the same, or something radically different? Come listen to the experts foretelling the future.


* Rob Aitken (ARM, US)
* Rohit Kapur (Synopsys, US)
* Janusz Rajski (Mentor Graphics, US)
* Jochen Rivoir (Agilent Technologies, DE)
* Robert Ruiz (Novas, US)
* Mike Tegethoff (Cadence, US)

TUESDAY MAY 23, 2006
08:30-10:00 Session 8A: BIST and Test Data Compression for Logic
Moderators: S. Hellebrand (Univ. of Paderborn, DE) and Z. Peng (Linköpings Univ., SE)

On-Chip Test Generation Using Linear Subspaces
R. Das, I.L. Markov, J.P. Hayes (Univ. of Michigan, US)

Convolutional Compactors with Variable Polynomials
A. Pogiel (Poznan Univ., PL), J. Rajski (Mentor Graphics, US), J. Tyszer (Poznan Univ., PL)

Deterministic Logic BIST for Transition Fault Testing
V. Gherman, H.-J. Wunderlich (Univ. Stuttgart, DE), J. Schlöffel, M. Garbers (Philips Semiconductors, DE)

08:30-10:00 Session 8B: Test of Sigma-Delta Modulators
Moderators: S. Bernard (LIRMM, FR) and A. Osseiran (Edith Cowan Univ., AUS)

Experimental Validation of a Fully Digital BIST for Cascaded SD Modulators
G. Leger, A. Rueda (Inst. de Microelectrónica de Sevilla, ES)

Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
E. Schüler, D. Scain Farenzena, L. Carro (UFRGS, BR)

Bit-stream Manipulation for SD Modulator Failure Mode Detection
K. Georgopoulos, A. Lechner, A. Richardson, M. Burbidge (Lancaster Univ., UK)

08:30-10:00 Vendor Session 8C: Memory and IDDQ Testing
Moderators: J. Figueras (Univ. Polit. de Catalunya, ES) and B. Kruseman (Philips Research, NL)

Design for Yield with Embedded Tester for Memory Subsystem in SoC
R. Chandramouli (Virage Logic, US)

Demystifying Repairable Memory
R. Aitken (ARM, US)

IDD(Q) Application to Analog and Mixed-Mode Circuits - A Case Study
S. Jing, A. Mathie, J. Garrison (National Semiconductor, US), H. Manhaeve (Q-Star Test, BE)

10:00-11:00 Session 9: Posters and Coffee/Tea Break

Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Resistive Bridging Fault Model and n-Detect Test
S. Biswas, A. Patra, S. Mukhopadhyay, D. Sarkar (IIT Kharagpur, IN)

Outliers Screening with Multiple Parameter Correlation Testing for Analogue ICs
L. Fang, M. Lemnawar, Y. Xing (Philips Semiconductors, NL)

Failure Mechanisms due to Process Variations in Nanoscale SRAM Core-Cells
P. Girard, S. Pravossoudovitch, A. Virazel (LIRMM, FR), M. Bastian (Infineon Technologies, FR)

An Information-Redundant Scheme for On-Line Testing of an Asynchronous ALU Operation
M.J. Marshall, G. Russell (Univ. of Newcastle-upon-Tyne, UK)

An Approach to Reduce Over-testing of Path Delay Faults in Data Paths Using RTL Information
Y. Yoshikawa, S. Ohtake, H. Fujiwara (Nara Inst. of Science and Tech., JP)

Detecting Hard-Faults Masked by Manufacturing Process Variations: a DAC Example
C. Wegener, M.P. Kennedy (Univ. College Cork, IRL)

On the Use of Multi-Clock, Multi-VDD and Multi-Temperature Schemes to Improve Dynamic Fault Detection in Digital Systems
Marcial Rodriguez-Irago, J.J. Rodriguez Andina (Univ. of Vigo, ES), F. Vargas (PUCRS, BR), J. Semião (Univ. Algarve, PT), I. Teixeira, J.P. Teixeira (IST/INESC-ID, PT)

A Parallel Multilevel-Huffman Decompression Scheme for IP Cores with Multiple Scan Chains
X. Kavousianos (Univ. of Ioannina, GR), E. Kalligeros, D. Nikolos (Univ. of Patras, GR)

Effects of Multiple Non-Concurrent Faults on Microprocessor Operation
E. Touloupis, J.A. Flint, V.A. Chouliaras (Loughborough Univ., UK), D.D. Ward (MIRA, UK)

11:00-12:30 Session 10A: Current-Based and Power Switch Testing
Moderators: P. Muhmenthaler (Infineon Technologies, DE) and J.L. Huertas Diaz (CNM, ES)

Testing and Diagnosis of Power Switches in SOCs
S.K. Goel, M. Meijer, J. Pineda de Gyvez (Philips Research, NL)

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications
M. Cimino, H. Lapuyade, M. De Matos, T. Taris, Y. Deval, J.B. Bégueret (IXL Laboratory, FR)

Detecting Subtle IDDQ Faults by Using an Optimized Model-Based Estimator
J. Schat (Philips Semiconductors, DE)

11:00-12:30 Session 10B: Test of AD and DA Circuits
Moderators: A. Chatterjee (Georgia Inst. of Tech., US) and A. Richardson (Univ. of Lancaster, UK)

 "Analogue Network of Converters": A DFT Technique to Test a Complete set of ADCs and DACs Embedded in a Complex SiP or SOC
V. Kerzérho (LIRMM, FR), P. Cauvet (Philips Semiconductors, FR), S. Bernard, F. Azaïs, M. Comte, M. Renovell (LIRMM, FR)

Reducing Sampling Clock Jitter to Improve SNR Performance of A/D Converters in Production Test
S. Goyal, A. Chatterjee (Georgia Inst. of Tech., US), M. Atia (National Semiconductor, US)

Design-Based Structural Test Method for Stereo DAC
L. Ma, G. Seuren, R. van Rijsinge, C. Bastiaansen, L. van der Dussen (Philips Semiconductors, NL)

11:00-12:30 Vendor Session 10C: Quality Cars, Quality Cell Phones, and Quality Research
Moderators: R. Aitken (ARM, US) and B. Bennetts (Bennetts Associates, UK)

Improving Automotive IC Quality - A Case Study on the Implementation of Advanced IDDQ Strategies Targeting Product Quality Improvement, Burn-In Elimination and Test Cost Reduction
M. Schmid, R. Flassak, A. Patitz (Dialog Semiconductor, DE), H. Manhaeve (Q-Star Test, BE)

High-Efficiency Multi-Site Test for SiP Mobile Technologies
J. McEleney (Teradyne, US)

Involving Academia in Leading Edge Semiconductor Test Technology
P. Roddy (Advantest America, US)

12:30-14:00: Lunch
14:00-15:00 Embedded Tutorial Session 11A
Moderator: P. Harrod (ARM, UK)
  Wafer Level Reliability Screens for Advanced CMOS
P. Maxwell (Avago Technologies, US)
14:00-15:00 Embedded Tutorial Session 11B
Moderator: T. Williams (Synopsys, US)
  Soft-Error Rate Testing of Deep-Submicron ICs
T. Heijmen, A. Nieuwland (Philips Research, NL)
14:00-15:00 Embedded Tutorial Session 11C
Moderator: N. Nicolici (McMaster Univ., CAN)
  New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)
B. Eklow (Cisco Systems, US), B. Bennetts (Bennetts Associates, UK)
15:30-24:00: Social Event
08:30-10:00 Session 12A: Automatic Test Pattern Generation
Moderators: S. Kajihara (Kyushu Inst. of Tech., JP) and F. Pöhl (Infineon Technologies, DE)

Fault Collapsing for Transition Faults Using Extended Transition Faults
I. Pomeranz (Purdue Univ., US), S. Reddy (Univ. of Iowa, US)

FATE: a Functional ATPG to Traverse Unstabilized EFSMs
G. Di Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli (Univ. di Verona, IT)

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults
N.B. Devta-Prasanna (Univ. of Iowa, US), A. Gunda, P. Krishnamurthy (LSI Logic, US), S. Reddy (Univ. of Iowa, US)


Session 12B: Advanced Analog Testing
Moderators: L. Carro (UFRGS, BR) and M. Renovell (LIRMM, FR)


 A Low-Cost Alternative Method for Harmonics Estimation in a BIST Context
V. Fresnaud, L. Bossuet, D. Dallet (Univ. of Bordeaux, FR), S. Bernard (LIRMM, FR), J.M. Janik (Univ. of Caen, FR), B. Agnus, P. Cauvet, Ph. Gandy (Philips Semiconductors, FR)

Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
B. Kim, H. Shin (Univ. of Texas-Austin, US), J.H. Chun (Intel, US), J. Abraham (Univ. of Texas-Austin, US)

Low-Cost Parametric Failure Diagnosis of RF Transceivers
D. Han, S. Bhattacharya, S. Goyal, A. Chatterjee (Georgia Inst. of Tech., US)

10:00-11:00 Session 13: Posters and Coffee/Tea Break

The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories
B. Halak, G. Russell (Univ. of Newcastle-upon-Tyne, UK)

On-Chip Micro Programmable BIST for High SRAM Test Coverage
R. Zappa, C. Selva, D. Rimondi, C. Torelli (STMicroelectronics, IT)

Diagnosis in Designs with Block Compactors
T. Clouqueur (Nara Inst. of Science and Tech., JP), K. Zarrineh (AMD, US), K.K. Saluja (Univ. of Wisconsin-Madison, US), H. Fujiwara (Nara Inst. of Science and Tech., JP)

Estimation of RF IC Specifications Based on DC Tests
S. Ellouz, P. Gamand, C. Kelma (Philips Semiconductors, FR), B. Vandewiele (Philips Research, NL), B. Allard (Cegely Insa-Lyon, FR)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing
N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel (LIRMM, FR), H.-J. Wunderlich (Univ. Stuttgart, DE)

A CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization
A. Bounceur, S. Mir (TIMA Laboratory, FR), L. Rolíndez (ST Microelectronics, FR), E. Simeu (TIMA Laboratory, FR)

Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies
S. Hamdioui, Z. Al-Ars, G. Gaydadjiev (Delft Univ. of Tech., NL), J.D. Reyes (Intel, US)

Fault Tolerance Against SEUs using Memory-Based Circuits to Improve the Architecture Vulnerability Factor
E. Rhod, C. Lisbôa, A. Michels, L. Carro (UFRGS, BR)

Stuck-At Fault Testing of FPGA Cores using Standard Test Pattern Generation Tools
M. Bennebroek, H. Vranken, A. Danilin (Philips Research, NL)

11:00-12:30 Session 14A: Test of Asynchronous and NOC Circuitry
Moderators: K. Chakravadhanula (Cadence Design Systems, US) and A. Yakovlev (Newcastle Univ., UK)

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
A. Amory (UFRGS, BR), K. Goossens, E.J. Marinissen (Philips Research, NL), M. Lubaszewski (UFRGS, BR), F. Moraes (PUCRS, BR)

A DFT Architecture for Asynchronous Networks-on-Chip
X.-T. Tran, J. Durupt, F. Bertrand (CEA-LETI, FR), C. Robach, V. Beroulle (INPG/ESISAR, FR)

Low-Cost Online Testing of Asynchronous Handshakes
D. Shang, A. Yakovlev, F. Burns, F. Xia, A. Bystrov (Univ. of Newcastle-upon-Tyne, UK)

11:00-12:30 Session 14B: Diagnosis
Moderators: H. Kerkhoff (Univ. Twente, NL) and J.-P. Teixeira (IST/INESC-ID, PT)

Test-per-Clock Detection, Localization and Identification of Interconnect Faults
M. Kopec, T. Garbolino, K. Gucwa, A. Hlawiczka (Silesian Univ. of Tech., PL)

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture
F. Pöhl (Infineon Technologies, DE), J. Rzeha (Univ. of Potsdam, DE), M. Beck (Infineon Technologies, DE), M. Gössel (Univ. of Potsdam, DE), R. Arnold, P. Ossimitz (Infineon Technologies, DE)

CMOS Defects Analysis using DefSim Measurement Environment
W.A. Pleskacz, T. Borejko, A. Walkanis (Warsaw Univ. of Tech., PL), V. Stopjakova (Slovak Univ. of Tech., Slovakia), A. Jutman, R. Ubar (Tallinn Univ. of Tech., EST)

12:30-14:00: Lunch
14:00-15:30 Session 15: Industrial Case Studies
Moderators: L. Bouzaida (STMicroelectronics, FR) and P. Varma (Blue Pearl Software, US

Implementing the Gate Delay Test Method on a DECT Base-Band Design
J. ten Pierick (Philips Semiconductors, CH)

SiP Testing - An Industrial Case Study
H. Eichinger, G. Scheer (Infineon Technologies, AU)

An Industrial Approach to Re-order Integrated Circuit Tests to Maximize Test Benefit
S. Krishan, A. Zjajo (Philips Research, NL)

15:30 Closing Remarks and Introduction to ETS'07
by B. Becker (Univ. of Freiburg, General Chair ETS'07)
15:45: End of Symposium



Organization Committee

General Chair

Bashir Al-Hashimi - Univ. Southampton (UK)

General Vice Chair

Bernd Becker - Univ. Freiburg (D)

Finance Chair

Peter Wilson - Univ. Southampton (UK)

Local Arrangements

Mark Zwolinksi - Univ. Southampton (UK)

Program Committee

Program Chair

Erik Jan Marinissen - Philips Research (NL)

Program Vice Chair

Hans-Joachim Wunderlich - Univ. Stuttgart (D)

Topic Chairs

Bernd Becker - Univ. Freiburg (D)
Sybille Hellebrand - Univ. Paderborn (D)
Hans Kerkhoff - Univ. Twente (NL)
Bram Kruseman - Philips Research (NL)
Cecilia Metra - Univ. Bologna (I)
Michel Renovell - LIRMM (F)
Jochen Rivoir - Agilent Techn. (D)
Jerzy Tyszer - Poznan Tech. Univ. (PL)

Publications Chair

Christian Landrault - LIRMM (F)

Panel Chair

Paolo Prinetto - Polit. Torino (I)

Tutorials Chair

Peter Harrod - ARM (UK)

Industrial Relations

Ben Bennetts - Bennetts Associates (UK)

Student Forum Chairs

Erik Larsson - Linkopings Univ. (SE)
Nicola Nicolici - McMaster Univ. (CAN)

Regional Liaisons

Luigi Carro - UFRGS (BR)
Krishnendu Chakrabarty - Duke Univ. (USA)
Adam Osseiran - Edith Cowan Univ. (AUS)
Cheng-Wen Wu - National Tsing-Hua Univ. (TW)


Einar J. Aas - Norw. Univ. of Science (N)
Dean Adams - Magma Design Automation (USA)
Rob Aitken - ARM Artisan (USA)
Walter Anheier - Bremen Univ. (D)
Florence Azaïs - LIRMM (F)
Luz Balado - Univ. Polit. de Catalunya (E)
Alfredo Benso - Polit. di Torino (I)
Gunnar Carlsson - Ericsson (S)
Wilfried Daehn - HS Magdbg.-Stendal (D)
Rainer Dorsch - IBM Entw. (D)
Joan Figueras - Univ. Polit. de Catalunya (E)
Marie-Lise Flottes - LIRMM (FR)
Graeme Francis - Philips Semiconductors (UK)
Hideo Fujiwara - NAIST (J)
Franco Fummi - Univ. Verona (I)
Patrick Girard - LIRMM (F)
Dimitris Gizopoulos - Univ. Piraeus (GR)
Michael Goessel - Potsdam Univ. (D)
Elena Gramatova - Slov. Acad. Sci. (SK)
Chris Hill - Mentor Graphics (UK)
Moktar Hirech - Synopsys (USA)
Andrzej Hlawiczka - Silesian TU. (PL)
Jose Luis Huertas Diaz - CNM (E)
Paul Hughes - ARM (UK)
Andre Ivanov - Univ. British Col. (CAN)
Rohit Kapur - Synopsys (USA)
Seiji Kajihara - Kyushu Inst. Tech. (J)
Helmut Lang - Freescale Semi. (D)
Marcelo Lubaszewski - UFRGS (BR)
Yiorgis Makris - Yale Univ. (USA)
Hans Manhaeve - QStar Test (B)
Tiziana Margaria - Univ. Göttingen (D)
Peter Maxwell - Agilent Techn. (USA)
Liviu Miclea - Univ. Cluj-Napoca (RO)
Salvador Mir - TIMA CMP (F)
Yukiya Miura - Tokyo Metro. Univ. (J)
Will Moore - Oxford Univ. (UK)
Peter Muhmenthaler - Infineon Techn. (D)
Franc Novak - Jozef Stephan Inst. (SLO)
Ondrej Novak - Tech. Univ. Liberec (CZ)
Alex Orailoglu - UCSD (USA)
Sule Ozev - Duke Univ. (USA)
Antonis Paschalis - Univ. Athens (GR)
Andras Pataricza - Budapest Univ. TE (H)
Zebo Peng - Univ. Linköping (S)
Frank Poehl - Infineon Techn. (D)
Jaan Raik - Tallinn Univ. (EE)
Janusz Rajski - Mentor Graphics (USA)
Andrew Richardson - Lancaster Univ. (UK)
Adoracion Rueda - CNM (E)
Chantal Robach - ESISAR (F)
Paul Rosinger _ Univ. Southampton (UK)
Bruno Rouzeyre - LIRMM (F)
Gordon Russell - Newcastle Univ. (UK)
Pablo Sanchez - Univ. Cantabria (E)
Jaume Segura - Univ. Illes Balears (E)
Adit Singh - Auburn Univ. (USA)
Matteo Sonza Reorda - Polit. Torino (I)
Bernd Straube - EAS/IIS FhG (D)
Joao-Paulo Teixeira - IST/INESC (P)
Nur Touba - Univ. of Texas (USA)
Raimund Ubar - Tallinn Univ (EE)
Bart Vermeulen - Philips Research (NL)
Carsten Wegener - Univ. College Cork (IRL)

Steering Committee


Christian Landrault - LIRMM (F)


Joan Figueras - Univ. Polit. de Catalunya (E)
Dimitris Gizopoulos - Univ. Piraeus (GR)
Erik Jan Marinissen - Philips Research (NL)
Peter Muhmenthaler - Infineon Technologies (D)
Antonis Paschalis - Univ. Athens (GR)
Zebo Peng - Linkopings Univ. (S)
Paolo Prinetto - Polit. Torino (I)
Michel Renovell - LIRMM (F)
Joao-Paulo Teixeira - IST/INESC (P)
Hans-Joachim Wunderlich - Univ. Stuttgart (D)
Yervant Zorian - Virage Logic (USA)

For more information, visit us on the web at:

The 11th IEEE European Test Symposium (ETS'06) is organized by the University of Southampton and sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

IEEE Computer Society- Test Technology Technical Council

University of British Columbia- Canada
Tel. +1-604-822-6936

Yervant ZORIAN
Virage Logic- USA
Tel. +1-510-360-8035

LIRMM- France
Tel. +33 467 418 523

Auburn University- USA
Tel. +1-334-844-1847

Rajesh K. GUPTA
University of California, Irvine- USA
Tel. +1-949-824-8052

Cheng-Wen WU

National Tsing Hua Univ.- Taiwan
Tel. +886-3-573-1154

Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica- Mexico

Nara Inst. of Science and Technology- Japan
Tel. +81-74-372-5220

Federal Univ. of Rio Grande do Sul (UFRGS)- Brazil
Tel. +34-93-401-6603

William R. MANN
Tel. +1-949-645-3294

Auburn University- USA
Tel. +1-334-844-1847

Yervant ZORIAN
Virage Logic, Inc.- USA
Tel. +1-510-360-8035


Politecnico di Torino- Italy
Tel. +39-011-564-7007

Auburn University- USA
Tel. +1-334-844-1847

LIRMM- France
Tel. +33-4-674-18524

Artisan Components- USA
Tel. +1-408-548-3297

Yervant ZORIAN
Virage Logic, Inc.- USA
Tel. +1-510-360-8035


Univ. of Piraeus- Greece
Tel. +30-210-414-2372


Synopsys- USA
Tel. +1-650-934-1487

Univ. Politècnica de Catalunya- Spain
Tel. +55-51-228-1633, Ext. 4830

Ibrahim HAJJ
American University of Beirut- Lebanon
Tel. +961-1-341-952

iRoC Technologies- Greece
Tel. +33-4-381-20763

Alfredo BENSO
Politecnico di Torino- Italy
Tel. +39-011-564-7080

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