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Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST
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CALL FOR SUBMISSIONS
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The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three- dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products. The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC). Topic Areas – You are invited to participate and submit your contributions to the 3DC-TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:
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Submission Instructions - Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Publications - 3DC-TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest (EWD), which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3DC-TEST Workshop. |
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Submission deadline: September 28, 2020 (23:59h PDT) Notification of acceptance: October 1, 2020 Early registration deadline: October 5, 2020 Camera-ready material: October 23, 2020 (23:59h PDT) |
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Additional Information | |
General Co-Chair: Erik Jan Marinissen – imec Kapeldreef 75 3001 Leuven, Belgium Tel.: +1 32 16-288755 Yervant Zorian – Synopsys Program Chair: Bapi Vinnekota – Broadcom 270 Innovation Drive San Jose, CA, USA Tel.: +1 (408) 922-1072 |
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Committee | |
General Co-Chairs:
Program Chair:
Finance Chair:
Industrial Chair:
Panel Chair:
Virtualization Chair:
Publicity Chair:
Web Chair:
Program Committee Members:
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For more information, visit us on the web at: http://3dtest.tttc-events.org/ |
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The 3DC-TEST Workshop is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
IEEE
Computer Society-Test Technology Technical Council |
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