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Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST
(3D&Chiplet TEST)
November 6, 2020
virtual workshop, continuation of the popular 3D-TEST Workshop in conjunction with ITC / Test Week 2020



The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three- dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products. The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC).

Topic Areas – You are invited to participate and submit your contributions to the 3DC-TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:

  • Defects due to Wafer Thinning
  • Defects in Intra-Stack Interconnects
  • DfT Architectures for 3D-SICs
  • EDA Design-to-Test Flow for 3D-SICs
  • Failure Analysis for 3D-SICs
  • Fault-Tolerant Design for 3D-SICs
  • Handling and Testing Singulated Stacks
  • Interposer Testing
  • Known-Good Die / Stack Testing
  • Open Interfaces between Chiplets
  • Standards for Power/Heat Dissipation during Test
  • Pre-, Mid-, and Post-Bond Testing
  • Reliability of 3D-SICs
  • Stacking Yield of Dies, Interconnects, Redundancy & Repair
  • Standards for 3D Testing, incl. IEEE Std 1838
  • Supply Chain and Logistic Issues
  • System/Board Test Issues for 3D-SICs
  • Test Cost Modelling for 3D-SICs
  • Test Flow Optimization for 3D-SICs
  • Tester Architecture incl. ATE and BIST
  • Thermal/Mechanical Stress in 3D-SICs
  • Wafer Probing and Probe Marks of 3D-SICs


Submission Instructions - Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results.

Publications - 3DC-TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest (EWD), which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3DC-TEST Workshop.

Key Dates

Submission deadline: September 28, 2020 (23:59h PDT)

Notification of acceptance: October 1, 2020

Early registration deadline: October 5, 2020

Camera-ready material: October 23, 2020 (23:59h PDT)

Additional Information

General Co-Chair:

Erik Jan Marinissen – imec Kapeldreef 75

3001 Leuven, Belgium

Tel.: +1 32 16-288755

Yervant Zorian – Synopsys

690 East Middlefield Road Mountain View, CA, USA

Tel.: +1 (650) 584-7120

Program Chair:

Bapi Vinnekota – Broadcom

270 Innovation Drive

San Jose, CA, USA

Tel.: +1 (408) 922-1072


General Co-Chairs:

  • Erik Jan Marinissen – imec (BE)
  • Yervant Zorian – Synopsys (US)

Program Chair:

  • Bapi Vinnakota – Broadcom (US)

Finance Chair:

  • Chen-Huan Chiang – Intel (US)

Industrial Chair:

  • Marc Hutner – Teradyne (CAN)

Panel Chair:

  • E. Jan Vardaman – TechSearch (US)

Virtualization Chair:

  • Stefano di Carlo – Polit. Torino (IT)

Publicity Chair:

  • Françoise von Trapp–3DInCites (US)

Web Chair:

  • Hardi Selg – TU Tallinn (EE)

Program Committee Members:

  • Saman Adham – TSMC (CAN)
  • Michael Alfano – AMD (US)
  • Dave Armstrong – Advantest (US)
  • Sandeep Bhatia – Google (US)
  • Krish Chakrabarty – Duke Univ. (US)
  • Sreejit Chakravarty – Intel (US)
  • Kun Young Chung – Qualcomm (US)
  • Jon Colburn – Nvidia (US)
  • Eric Cormack – DfT Solutions (UK)
  • Adam Cron – Synopsys (US)
  • Alfred Crouch – Amida (US)
  • Marie-Lise Flottes – LIRMM (FR)
  • Ferenc Fodor – IMEC (BE)
  • Paul Franzon – NC State Univ. (US)
  • Phil Garrou – MCNC (US)
  • Sandeep K. Goel – TSMC (US)
  • Alan Hales – Texas Instruments (US)
  • Junlin Huang – HiSilicon (CN)
  • Hailong Jiao – Peking University (CN)
  • Gerard John – Amkor Technology (US)
  • Hongshin Jun – Juniper Networks (US)
  • Shuichi Kameyama – Ehime Univ. (JP)
  • Chien-Mo Li – NTU (TW)
  • Alan Liao – FormFactor (US)
  • Amit Majumdar – Xilinx (US)
  • Teresa McLaurin – ARM (US)
  • Benoit Nadeau-Dostie – Mentor (CAN)
  • Brandon Noia – AMD (US)
  • Christos Papameletis – Cadence (US)
  • Mike Ricchetti – Synopsys (US)
  • Saghir Shaikh – Broadcom (US)
  • Raffaele Vallauri – Technoprobe (IT)
  • Pascal Vivet – CEA-Leti (FR)
  • Michael Wahl – Univ. of Siegen (DE)
For more information, visit us on the web at:

The 3DC-TEST Workshop is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

IEEE Computer Society-Test Technology Technical Council

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