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IEEE VLSI Test Symposium 2016
CALL FOR PARTICIPATION
The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world’s leading test experts and professionals from both industry and academia join to present and debate key issues in testing. VTS 2016 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Embedded Tutorials, Panels, Hot Topic Sessions, Half-day Tutorials, and the Innovative Practices Track.
The core of VTS 2016, the three day technical program, responds to the many trends and challenges in the semiconductor design and manufacturing industries, with papers and contributions covering a diverse and seminal set of topics including: Analog, Mixed-Signal & RF Test; ATPG & Test Compression; Memory Testing, test Quality and Yield Optimization, Delay and Performance Testing; Reliability; Low Power, SOC testing, Test Applications: Hardware Security and Microfluidics BioChips, Thermal Issues in Test, Emerging Technologies for Hardware Security, Test Implications and Challenges in Near-Threshold Computing, Cell Aware testing, Post Production Tuning in RF Circuits, Innovations in Board Testing, Managing Lifetime in Manycore Systems, New emerging topics Hardware Security; System Validation and Silicon Debug; test and Fault Tolerance in Approximate Computing; 3D IC Test and IEEE 1687 Implementations.
The second keynote is a tribute to the late Prof. E.J. McCluskey, entitled Digital revolution over Generations. This keynote is given by a panel of three prominent speakers belonging to three different generations, from senior to freshly-graduating. They will highlight the impact of Ed's research on today's challenges and how they have benefited from working together with him as they had to address these challenges. The three speakers are Professor Jacob Abraham, Cockrell Family Regents Chair in Engineering, University of Texas at Austin, Dr. Hong Hao, Senior Vice President, Samsung, and Mr. Max Shulaker, Stanford University.
Full registration includes breakfasts, lunches, coffee breaks, social event, and electronic distribution of the symposium proceedings.
Registration page: http://www.regonline.com/2016ieeevlsitestsymposium
The IEEE VLSI Test Symposium will be held at the Caesars Palace, 3570 S Las Vegas Blvd, Las Vegas, NV 89109, USA.
Hotel Reservation Procedure:
Discounted rates are available until April 4, 2016 at 5pm PST or until the room block is sold out, whichever comes first. Click here to confirm a room: https://resweb.passkey.com/go/SCIIE6
For general information:
Yiorgos Makris University of Texas at Dallas email@example.com
For program information:
Lorena Anghel University of Grenoble-Alpes/TIMA firstname.lastname@example.org
Srivaths Ravi Texas Instruments email@example.com
Innovative Practices Track:
New Initiatives Chair:
Electronic Media Chair:
Corporate Support Chair:
For more information, visit us on the web at: http://www.tttc-vts.org
The IEEE VLSI TEST SYMPOSIUM is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
IEEE DESIGN & TEST EIC
ASIA & PACIFIC
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