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IEEE International Workshop on Defects, Adaptive Test, Yield and Data Analysis
SUBMISSION DEADLINE EXTENDED TO August 31, 2015
CALL FOR PAPERS
Every year, we revisit the scope of the DATA workshop to capture emerging issues, but the common theme has always been DATA, specifically, semiconductor test and yield data. We need to not only measure and collect data, but also to process the data appropriately for yield analysis. The data can come from a variety of source, including test sort & fail bins, in-line defect inspection, test measurements, memory bitmapping, scan diagnosis, and physical failure analysis. There is a need to aggregate, overlay, and cross-correlate the data from these various sources in a way that allows efficient yield learning and enables a speedy production ramp.
The Organizing Committee for the DATA-2015 Workshop is soliciting papers in the area of semiconductor yield analysis, learning, and improvement. Of particular interest are advanced techniques and new tools for faster data-driven yield learning, data acquisition, the statistical analysis of yield loss in semiconductor manufacturing, and implementation of adaptive test. Preference will be given to real-world case studies.
Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions and Poster style “Spot-Light” presentations describing industrial experiences or research are also invited.
To present at the workshop, send to firstname.lastname@example.org a PDF version of an extended abstract or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format ) by August 31, 2015. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on September 22, 2015.
Submission Date: August 31, 2015
Notification of Acceptance: September 10, 2015
Camera Ready Paper (.pdf): September 22, 2015
Final Presentation Slides (.ppt): October 1, 2015
Technical Program Submissions:
Southern Methodist University, USA.
Arani Sinha, Intel
Jennifer Dworak, SMU
Wesley Smith, Galaxy
Sankaran Menon, Intel
Kanad Chakraborty, Intel
Chintan Patel, UMBC
LOCAL ARRANGEMENTS CHAIR
David Park, OptimalPlus
TEST STANDARDS CHAIR
Al Crouch, ASSET InterTech
Paul Simon, Qualtera
Jeffrey Roehr, Texas Instruments
Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Star Test
Jim Plusquellic, U. New Mexico
Rob Aitken, ARM
Nemat Bidokhti, Cisco
Sreejit Chakravarty, Intel
John Carulli, GlobalFoundries
Patrick Girard, LIRMM, France
Ajay Khoche, Consultant
Mike Laisne, Qualcomm
Amit Nahar, TI
Suriyaprakash Natarajan, Intel
Jay Orbon, Consultant
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Claude Thibeault, ETS, Canada
Li C. Wang, UCSB
Xiaoqing Wen, KIT, Japan
Qiang Xu, CUHK, Hong Kong
For more information, visit us on the web at: http://DATA.tttc-events.org/
The IEEE International Workshop on Defects, Adaptive Test, Yield and Data Analysis is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
IEEE DESIGN & TEST EIC
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