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6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 

(3D-TEST'15) 
Oct 8/9 2015 
Will be held in conjunction with ITC 2015 at the Disneyland Hotel, Anaheim, CA  

http://3dtest.tttc-events.org

ERRATA: the previous message contained a wrong URL.
CALL FOR PARTICIPATION 

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
 
3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

Program Highlights

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The workshop program contains the following elements.


Keynote Addresses:

  • “New Paradigm Shift in 3-D Design and Testing” by Jeff Rearick – AMD, USA
  • “3D Integrated CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications” by K.-T. (Tim) Cheng – UC Santa Barbara, USA
  • “Known Good Die – Fantasy Land or Tomorrow Land?” by John Carulli and TM Mak – GLOBALFOUNDRIES, USA

Four sessions with in total 13 paper presentations.

Two panel-discussion sessions

  • Monolithic 3D: Will It Happen and If So, What Are The Test Challenges and Solutions?
  • Test Model Generation for JEDEC 3D Memories: Who Owns the Responsibility?
  • Continuous display of table-top demos. 

More information: http://3dtest.tttc-events.org

Registration and Accommodation 

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You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes access to all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments. 

On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org). Alternatively, register on-site during Test Week at the ITC Registration Counter at the Disneyland Hotel; admission for on-site registrants is subject to availability.

Additional Information 
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General Chair:
Yervant Zorian
Synopsys
700 East Middlefield Road Mountain View, CA, USA 
Tel.: +1 (650) 584-7120 
yervant.zorian@synopsys.com

Program Chair:
Erik Jan Marinissen
IMEC
Kapeldreef 75
B-3001 Leuven, Belgium 
Tel.: +32 16 28-8755 
erik.jan.marinissen@imec.be

Program Vice-Chair:
Shi-Yu Huang
National Tsing-Hua University
101, Sec. 2, Kuang-Fu Road
HsinChu, Taiwan
Tel.: +886 3-573-1147 
syhuang@ee.nthu.edu.tw

Committee 
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General Chair:

  • Y. Zorian – Synopsys (US)

Program Chair / Vice Chair:

  • E.J. Marinissen – IMEC (BE) S.-Y. Huang – NTHU (TW)

Finance Chair:

  • B. Eklow – Cisco Systems (US)

Panel Chair:

  • S.K. Goel – TSMC (US)

Publication Chair:

  • L. Ciganda – Politecnico di Torino (IT)

Publicity Chair:

  • F. von Trapp – 3DInCites (US)

Web Chair:

  • G. Jervan – Tallinn Univ. of Techn. (EE)

Arrangements Chair:

  • J. Potter – ASSET Intertech (US)

Program Committee Members:

  • S. Adham – TSMC (CAN)
  • V. Agrawal – Auburn Univ. (US)
  • S. Bhatia – Google (US)
  • K. Chakrabarty – Duke Univ. (US)
  • S. Chakravarty – Intel (US)
  • E. Cormack – DfT Solutions (UK)
  • A. Cron – Synopsys (US)
  • A. Crouch – ASSET InterTech (US)
  • P. Franzon – NC State Univ. (US)
  • S. Hamdioui – TU Delft (NL)
  • M. Higgins – Analog Devices (IRL) 
  • C.-L. Hsu – ITRI (TW)
  • M. Hutner – Teradyne (CAN)
  • L. Jiang – Shanghai JT Univ (CN)
  • H. Jiao – TU Eindhoven (NL)
  • H. Jun – SK hynix (KR)
  • S. Kameyama – Fujitsu (JP)
  • M. Knox – IBM (US)
  • M. Laisne – Qualcomm (US)
  • C.M. Li – NTU (TW)
  • M. Loranger – FormFactor (US)
  • A. Majumdar – Xilinx (US)
  • T.M. Mak – GlobalFoundries (US)
  • T. McLaurin – ARM (US)
  • B. Nadeau-Dostie – Mentor Graph. (US) 
  • B. Noia – AMD (US)
  • C. Papameletis – Cadence (US)
  • R. Parekhji – Texas Instruments (IN)
  • B. Patti – Tezzaron Semiconductor (US) 
  • M. Ricchetti – Synopsys (US)
  • S. Shaikh – Broadcom (US)
  • K. Smith – Cascade Microtech (US)
  • R. Vallauri – Technoprobe (IT)
  • P. Vivet – CEA-Leti (FR)
  • M. Wahl – Univ. Siegen (DE)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The 6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).



IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR 
Michael NICOLAIDIS 
TIMA Laboratory - France 
Tel. +33-4-765-74696 
E-mail michael.nicolaidis@imag.fr

PAST CHAIR 
Adit D. SINGH  
Auburn University - USA  
Tel.  +1-334-844-1847 
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR 
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR 
Michael Purtell
Intersil 
- USA 
Tel. +1-408-372-6015 
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN 
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI
 
Politecnico di Torino
 - Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES 
André IVANOV 
University of British Columbia - Canada 
Tel. +1-604-822-6936 
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA 
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD 
Yervant ZORIAN
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR 
André IVANOV 
University of British Columbia - Canada 
Tel. +1-604-822-6936 
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR 
Rohit KAPUR
 
Synopsys, Inc. 
USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE 
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC 
André IVANOV
U. of British Columbia Canada 
Tel. +1 
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS 
Chen-Huan CHIANG 
Alcatel-Lucent
 - USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES 
Matteo SONZA REORDA
Politecnico di Torino Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC 
Kazumi HATAYAMA
Gumma University - Japan
Tel.+81-277-30-1111
E-mail k-hatayama@el.gunma-u.ac.jp

LATIN AMERICA 
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA 
André IVANOV 
University of British Columbia - Canada 
Tel. +1-604-822-6936 
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA 
Università di Bologna - Italy
Tel. +39-051-209-3038 
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com


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