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6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
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CALL FOR PARTICIPATION
The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
Four sessions with in total 13 paper presentations.
Two panel-discussion sessions
More information: http://3dtest.tttc-events.org
You are invited to participate in the workshop. Participation requires registration and a registration fee. Workshop registration includes access to all technical sessions, Electronic Workshop Digest (containing extended abstracts, papers, slides, posters, as made available by their presenters), workshop reception, continental breakfast, lunch, and break refreshments.
On-line registration is available via the workshop’s website (http://3dtest.tttc-events.org). Alternatively, register on-site during Test Week at the ITC Registration Counter at the Disneyland Hotel; admission for on-site registrants is subject to availability.
Program Chair / Vice Chair:
Program Committee Members:
For more information, visit us on the web at: http://3dtest.tttc-events.org
The 6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
IEEE DESIGN & TEST EIC
ASIA & PACIFIC