TTTC Header Image
TTTC's Electronic Broadcasting Service

1st IEEE International Workshop on
Design for Manufacturability & Yield
(DFM&Y 2006)

October 26 27, 2006

Santa Clara Convention Center,
Santa Clara, California, USA

http://www.unipi.gr/dfmy/

CALL FOR PARTICIPATION

Scope -- Workshop At A Glance -- Committee Members -- Program -- Additional Information

Scope

top

Increased manufacturing susceptibility in today's nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools are proposed today. Some of which are leveraged during the back-end design stages, and others have post-design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today's SoC designs.

Workshop At A Glance

top

Thursday -- Friday

THURSDAY, OCTOBER 26
2:00 pm - 5:00 pm Registration
4:00 pm - 5:00 pm Opening Session
5:00 pm - 7:00 pm Session 1: DFM&Y and Test
7:00 pm - 9:00 pm Evening Reception
FRIDAY, OCTOBER 27
7:00 am - 8:00 am Continental Breakfast
8:00 am - 10:00 am Session 2: Context and Perspectives on DFM&Y
10:00 am - 10:30 am Break
10:30 am - 12:30 pm Session 3: DFM&Y and Physical Design
12:30 pm - 1:30 pm Lunch
1:30 pm - 3:30 pm

Session 4: Topics in DFM&Y

3:30 pm - 5:00 pm Session 5: Panel - "What Will Make or Break DFM&Y"

Committee Members

top

WORKSHOP COMMITTEE
General Chair
Yervant Zorian
Virage Logic

Co-General Chair
Juan-Antonio Carballo
IBM

Program Chair
Andrew B. Kahng
Blaze DFM

Publication
A. Ivanov
Univ British Columbia

Panels
R. Camposano
Synopsys

Finance
R. Aitken
ARM

Publicity
D. Gizopoulos
Univ Piraeus

PROGRAM COMMITTEE
D. Appello, ST Microelectronics
C. Bittlestone, Texas Instruments
A. Gattiker, IBM
K.S. Kim, Intel
F. Kurdahi, UC Irvine
H. Lee, Magma
A. Markosian, Ponte Solutions
D. Maynard, IBM
C. Metra, Univ of Bologna
S. Muddu, UC San Diego
M. Murakata, STARC
S. Nassif, IBM
M. Nicolaidis,TIMA
N. Ns, Texas Instruments
M. Orshansky, Univ of Texas
V. Pitchumani, Intel
J.M. Portal, Univ of Marseille
P. Prinetto, Pol. di Torino
R. Radojcic, Qualcomm
J. Rey, Mentor Graphics
K. Roy, Purdue Univ
A. Singh, Auburn Univ
D. Sylvester, Univ of Michigan
V. Vardanian, Virage Logic
B. Vermeulen, Philips
D.M.H. Walker, Texas A&M Univ
S. Wigley, LTX
C-W. Wu, National Tsing Hua Univ
H-J. Wunderlich, Univ of Stuttgart
G. Yeric, Synopsys

Workshop Program

top

Thursday -- Friday

THURSDAY, OCTOBER 26
2:00 pm - 5:00 pm Registration
4:00 pm - 5:00 pm

Opening Session

Welcoming Remarks
General Chair Y. Zorian, Virage Logic
Program Chair A. B. Kahng, UCSD

Keynote Address
"DFM&Y: Whose Problem is it Anyway?"
N. NS, Texas Instruments

5:00 pm - 7:00 pm

Session 1: DFM&Y and Test

Session Chair
Andre Ivanov
Univeristy of British Columbia

1.1 Test Structures for Process and Product Performances Evaluation
Fabrice Rigaud, J.M. Portal, H. Aziza, D. Nee, J. Vast and
C. Auricchio, ST Microlelectronics, U. of Marseille

1.2 Hardware Debug Infrastructure for Soc Featuring Embedded Configurable Logic
Stefano Pucillo, Lorenzo Cali and Stefania Stucchi, STMicroelectronics

1.3 Test Chip Methods for Successful DFM
Greg Yeric, Synopsys

1.4 Accounting for Chip Yield at the Application Level
Fadi Kurdahi, Ahmed Eltawil, Kang Yi, Young-Hwan Park, Amin
Khajeh Djahromi, and Yervant Zorian, UC Irvine and Virage Logic

Wrap up Discussion

7:00 pm - 9:00 pm Evening Reception
FRIDAY, OCTOBER 27
7:00 am - 8:00 am Continental Breakfast
8:00 am - 10:00 am

Session 2: Context and Perspectives on DFM&Y

Session Chair
Julie Segal
Spanion

2.1 DFM: State and Directions
Sunit Rikhi, Intel

2.2 Using Test as the Ultimate Measure of DFM Effectiveness
Bob Madge, LSI Logic

2.3 Advances on Proactive DFM Experiences
David Appello, ST Microelectronics

2.4 DFM&Y Research and Development topics in STARC
Masami Murakata, STARC

10:00 am - 10:30 am Break
10:30 am - 12:30 pm

Session 3: DFM&Y and Physical Design

Session Chair
Kazumi Hatayama
STARC

3.1 Lithography- and CMP-Aware Routing
David Pan, UT Austin

3.2 Manufacturing Models & Implementation Technology
Matt Liberty, Cadence

3.3 Manufacturability-Driven Physical Synthesis
Patrick Groeneveld, Magma

3.4 The Marriage of DFM and Physical Design: Can It Work?
Joe Hutt, Pyxis

3.5 Lithography-Aware Physical Design: Challenges and Opportunities
Xinying Zhang, Synopsys

12:30 pm - 1:30 pm Lunch
1:30 pm - 3:30 pm

Session 4: Topics in DFM&Y

Session Chair
Rene Segers
NXP

4.1 Simple and Accurate Models of Capacitance Increment
Due to Metal Fill, Youngmin Kim, U. Michigan

4.2 A Modeling Technique for Non-Rectangular Gates for Static Timing Analysis
Shayak Banerjee, UT Austin

4.3 A Yield Enhancement Technique for Standard Cell Libraries
Ara Aslyan, Ponte Solutions

4.4 Fast Dual Graph-Based Hotspot Detection
Chul-Hong Park, UC San Diego

4.5 DFM Framework for Dynamic Yield Optimization
Fedor Pikus, Mentor Graphics

4.6 Yield Prediction Using Via Distribution Model
Takumi Uezono, Tokyo Institute of Technology

3:30 pm - 5:00 pm

Session 5: Panel - "What Will Make or Break DFM&Y"

Co-Organized with: IEEE Design & Test of Computer

Moderator
Gary Smith
Gartner Dataquest

Panelists:
Rob Aitken, ARM
Juan-Antonio Carballo, IBM
Andrew Kahng, UC San Diego
Ara Markosian, Ponte Solutions
Masami Murakata, STARC
David Overhauser, Overhauser-Li Consultancy
David Pan, UT Austin
Yervant Zorian, Virage Logic

Additional Information

top

WORKSHOP LOCATION
DFM&Y 2006 will be held at Santa Clara Convention Center, Santa Clara, California, USA, October 26 - 27, 2006, immediately following ITC 2006 (www.itctestweek.org).

REGISTRATION
All Workshop participants require registration. Please register using the ITC 2006 Registration Forms.

SPECIAL ISSUE
The best contributions of DFM&Y 2006 will appear in a Special Issue of JETTA (the Journal of Electronic Testing: Theory and Applications).

INFORMATION CONTACTS
For more information on the Workshop, please contact:
Yervant ZORIAN
y.zorian@computer.org

Website
http://www.unipi.gr/dfmy

TTTC Office:
IEEE TTTC
1474 Freeman Dr
Amissville, VA 20106 USA
Tel: +1-540-937-8280
Fax: +1-540-937-7848
Email: tttc@computer.org

For more information, visit us on the web at: http://www.unipi.gr/dfmy

The 1st IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2006) is sponsored by the IEEE Computer Society Test Technology Technical Council, in Cooperation with CEDA - IEEE Council on Electronic Design Automation and in Conjunction with Test Week / Interntional Test Conference 2006 (ITC 06).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Joan FIGUERAS
Universitat Politècnica de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Scott DAVIDSON
Sun Microsystems
- USA
Tel. +1-650-786-7256
E-mail scott.davidson@eng.sun.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies - France
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


This message contains public information only. You are invited to copy and distribute it further.

For more information contact the TTTC office or visit http://tab.computer.org/tttc/

To remove your name from this mailing list, please email unsubscribetttc@cemamerica.com or login to the TTTC Database and uncheck the EBS (Electronic Broadcast Service) box, which can modified by selecting "Edit" next to "My Subscriptions".