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IEEE International Workshop on
Held in Conjunction with ITC Test Week (ITC 2006)
PRELIMINARY CALL FOR PAPERS
Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing a SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools are proposed today. Some of these are leveraged during the back-end design stages, and others have post-design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment, and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.
Representative topics include, but are not limited to:
To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (500 words) or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.
Submit a copy of your paper proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than August 15, 2006.
Submit your paper proposal to:
Authors will be notified of the disposition of their papers by September 15, 2006.
Authors of accepted papers may submit an illustrated text by October 1, 2006 for inclusion in the Digest of Papers, which will be provided to the attendees.
Special Issue: The best contributions of DFM&Y 2006 will appear in a Special Issue of JETTA (the Journal of Electronic Testing: Theory and Applications).
For general information contact:
Program Committee to include
D. Appello, STMicroelectronics
For more information, visit us on the web at: http://www.unipi.gr/dfmy
The 1st IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society– Test Technology Technical Council
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