TTTC’s E. J. McCluskey Doctoral Thesis Award

The Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. The Award is given to the winner of a two-stage contest with semi-finals held at TTTC-sponsored conferences, symposia or workshops. The winners of the semi-finals, determined by jurys composed of industrial experts, will compete against each other in the finals, held at a major TTTC-sponsored conference or symposium. This major Award is named after Prof. Edward J. McCluskey, a key educator and mentor in the fields of test technology, logic design, and reliability.

Call for Participation 2021

We are happy to announce that in 2021, the Contest will be coming held in 4 locations: the  Asian Test Symposium, the European Test Symposium, the Latin-America Test Symposium and the  VLSI Test Symposium


Because of ATS being held after or really close to ITC, the Asian semi-final for the TTTC’s E. J. McCluskey Doctoral Thesis Award is usually held the year before.


All active doctoral students working on test-related topics and recent graduates who graduated 2019 or later are eligible for the Award. An individual can only participate in the contest once in a lifetime. Prospective participants are encouraged to participate when they are close to thesis completion and have obtained sufficient results. Prospective contestants submit a summary of their thesis work (up to 2000 words), possibly accompanied by one additional page of figures and references. They are free to submit up to three published referenced as supporting material, which are considered by the jury on an optional basis. The abstract should clearly address the following:

  • define the problem and its relevance to industry,
  • describe existing industrial practices for solving the problem, and
  • explain the proposed methodology (and any pertinent case study) and how it advances the theory and/or practice in the particular field.
  • A student can freely choose the regional (semi-finals) site to submit the summary. Submissions to multiple regional sites are prohibited.


The 4 semi-finals sites for the Best Doctoral Thesis Award 2021:

  1. VLSI Test Symposium 2021 (VTS’21), local coordinator Karimi Naghmeh
  2. European Test Symposium 2021 (ETS’21), local coordinator Alberto Bosio, Alessandro Savino
  3. Latin Americ Test Symposium 2021 (LATS’21), local coordinator José Lipovetzky
  4. Asian Test Symposium 2020 (ATS’20), local coordinator Hiroshi Takahashi

For submission information, please refer to the Local Coordinator at the conference website.

For general inquiries, direct your questions to the Global Coordinator,  Michele Portolan (Grenoble-INP, France).


Based on the submitted abstracts, a set of semi-finalists will be selected for the semi-finals of the contest. Semi-finals could be canceled if the numbers of submissions is inadequately low, in which case candidates will be invited to take part in another semi-final. This round includes a short (seven-minute) slot for oral presentation during a dedicated session at the semi-final event. The jury will judge the presentations, and the winner of the semi-final will be announced during the event.

The finalists will present their work in a 30-minute presentation at ITC’21, and the winner will be determined by a panel of academic and industrial experts. The Award is given to the winning student and the advisor of the thesis.

Mohammad Nasim Imtiaz Khan (The Pennsylvania State University), USA 2020 1st Place Winner Assuring Security and Reliability of Emerging Non-Volatile Memories VTS
Sarah Azimi, Politecnico di Torino, Italy 2020 Runner-Up Digital Design Techniques for Dependable High Performance Computing ETS
Rajit Karmakar , Department of E&ECE, Indian Institute of Technology Kharagpur, India 2020 Runner-Up Hardware IP Protection Using Logic Encryption and Watermarking ATS
Rafael B. Schvittz – Federal University of Pelotas – UFPEL, Brazil 2020 Runner-Up Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients LATS
Tao Chen (Iowa State University), USA 2019 1st Place Winner Thesis title: Built-in Self-Test and Self-Calibration for Analog and Mixed Signal Circuits VTS
Innocent Okwudili, Delft University of Technology, Netherlands 

2019 Runner-Up Reliability Modeling and Mitigation

for Embedded Memories