Context & Motivation:
Semiconductor memories are inherent parts of modern System-on-Chip (SoC) designs. Due to the increase in computing capacity, a proportional increase in the amount of data to be processed is observed in SoCs, thus creating larger memory capacity requirements. The latest technologies make these memories denser and thus defects due to the manufacturing process are more prone to occur not only in the memory array but also in the periphery of the memory.
Magnetic Random Access Memory (MRAM) is one of the most mature emerging technology considered in several industrial demonstrators by major semiconductor foundries. In this technology, data is stored in terms of resistive states by using the spin of electrons for storage instead of their charge. MRAM has several characteristics that make it useful for many applications (automotive, health, security, etc.), such as non-volatility, fast access time, zero leakage power of the memory array, endurance, reliability and CMOS-process compatibility.
Memory test is currently based on the use of March algorithms targeting Functional Fault Models (FFMs). However, with shrinking technologies, these solutions will shortly become insufficient to achieve high coverage of new defect types that may occur during the manufacturing process. One solution to this problem is to adapt Cell-Aware (CA) test concepts successfully developed and fully deployed for logic circuits to non-volatile MRAM memories. CA test assumes that many escapes during testing are due to defects within standard cells. CA test uses a cell-internal-fault dictionary (called CA model) describing the detection conditions of each potential defect affecting a standard cell.
By adapting innovations from the digital world to emerging memory testing, and by replacing functional testing of MRAM memories by structural testing, this project will satisfy two objectives: anticipate the widening gap between correct functional modeling and realistic behavior of defects in memories, and consider new failure mechanisms in MRAM emerging technologies that cannot always be modeled by FFMs due to the stochastic nature of the switching and the inherent thermal instability of MRAMs.
Objectives:
The goal of the PhD thesis is hence to develop test characterization models (i.e., CA models) for the gate-cells (elementary cells, simple and complex logic gates) extracted from the description of an MRAM memory. These models will be enriched with layout information to allow complete coverage of realistic defects. Considering the significant number and the diversity of gate-cells for all considered memory technologies, Machine Learning techniques will be used for the automated generation process of these models in a time-efficient manner.
Keywords:
Magnetic Memories, Defect, Characterization models, Test, Diagnosis, Quality, Machine Learning
Required skills:
The applicant must have a Master and/or an Engineering degree, with skills in the fields of artificial intelligence, digital circuit design, and test of circuits and systems. Good knowledge of programming languages (Python, Matlab, etc.) and CAD tools (Synopsys, Cadence) is also mandatory.
Funding and partners:
The PhD thesis will be funded through a doctoral contract allocated by the CNRS in the framework of the Call « 80PRIME » 2021. The work will be done in collaboration between LIRMM (UMR 5506 Université de Montpellier / CNRS), SPINTEC (UMR 8191 CEA / CNRS / Université Grenoble-Alpes / Grenoble INP) and STMicroelectronics (Crolles).
LIRMM, 161 rue Ada, 34095 Montpellier, France http://www.lirmm.fr/
SPINTEC, 17 rue des Martyrs, 38054 Grenoble, France http://www.spintec.fr/
STMicroelectronics, 850 Rue Jean Monnet, 38920 Crolles, France https://www.st.com/
Starting date / duration / location:
September 2021 / 3 years / Montpellier & Grenoble
Contact at LIRMM:
Patrick GIRARD, girard@lirmm.fr, Tel. +33 467 41 86 29
Contact at SPINTEC:
Lorena ANGHEL, lorena.anghel@phelma.grenoble-inp.fr , Tel. +33 438 78 44 16
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Context & Motivation:
Today’s computer architectures for processing "Big Data" information induce significant energy consumption and calculation times. A significant part of these costs is due to the exchanges between storage elements, where the data are stored, and computation nodes. This cost is exacerbated by "cache" memory systems generally used to reduce computer run times but which greatly contribute to the energy budget. To cope with this explosion of data and their cost of processing, the scientific community is now exploring computing architectures representing a breakthrough in this area. These architectures rely on the capabilities of new integration technologies to perform computations directly into the memory instead of deporting data to an external computing node and then storing the result. The goal is to increase the performances and to reduce the energy consumption induced by operations on a large amount of data. Recent advances in the design of volatile and non-volatile memories, and their implementation using emerging technologies, make it possible to envisage the realization of compact devices, time efficient with low energy consumption, where the computation can be carried out within the memory and thus without any exchange with an external computation node. This emerging computing paradigm is called In-Memory Computing (IMC). As all integrated electronic systems, IMC architectures must be tested. The test phase, applied after manufacturing, is prepared and built during the design phases of the IMC-based integrated electronic system. Test allows to check the correct functioning of the system and therefore to guarantee its reliability during its life time.
Objectives:
The goal of the PhD thesis is to develop test solutions to improve the reliability of in-memory computing architectures. The main expected results of the project relate to the development of test and design methodologies for the reliability of in-memory computing architectures.
Keywords:
In-Memory Computing, Memory technologies, SRAM, Test, Reliability.
Required skills:
The applicant must have a Master and/or an Engineering degree, with skills in the fields of digital circuit design and test of circuits and systems. Good knowledge of programming languages (Python, Matlab, etc.) and CAD tools (Synopsys, Cadence) is also mandatory.
Funding and partners:
The PhD thesis will be funded through a doctoral contract allocated by the doctoral school I2S of the University of Montpellier and the Occitanie Region. The work will be done in collaboration between LIRMM (UMR 5506 University of Montpellier / CNRS) and CEA-Leti (Grenoble):
LIRMM, 161 rue Ada, 34095 Montpellier, France http://www.lirmm.fr/
CEA-Leti, 17 avenue de Martyrs, 38054 Grenoble http://www.leti-cea.fr/
Starting date / duration / location:
October 2021 / 3 years / Montpellier & Grenoble
Contacts:
Arnaud VIRAZEL, Associate Professor University of Montpellier, virazel@lirmm.fr, Tel. +33 (0) 4 67 41 85 76
Marie-Lise FLOTTES, CNRS Researcher, flottes@lirmm.fr, Tel. +33 (0) 4 67 41 86 35
Patrick GIRARD, CNRS Research Director, girard@lirmm.fr, Tel. +33 (0) 4 67 41 86 29
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