International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
(DFT 2021)
October 6th - 8th, 2021
Virtual event

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following:

Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.

Design For Testability in IC Design: FPGA, SoC, NoC, ASIC, low power design, and microprocessors.

Error Detection, Correction, and Recovery: Self-testing and self-checking solutions; error-control coding; fault-masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.

Dependability Analysis and Validation: Fault injection techniques and frameworks; dependability and characterization.

Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.

Radiation effects: SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.

Defect and Fault Tolerance: Reliable circuit/system synthesis; fault-tolerant processes and design; design space exploration for dependable systems, transient/soft faults.

Aging and Lifetime Reliability: Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.

Dependable Applications and Case Studies: Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.

Emerging Technologies: Techniques for 2.5D/3D ICs, quantum computing architectures, memristors, spintronics, microfluidics, etc.

Design for Security: Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Paper Submission: authors are invited to submit original and unpublished contributions in the areas described above. Submitted papers should be no longer than 6 pages and adhere to the IEEE conference template, 2­columns style (available on conference web site). Papers can be accepted as regular papers (former oral presentations) or short papers (formerly posters). Both types of paper will be included in the IEEE proceedings; the page limit for proceedings is 6 pages for regular papers and 4 pages for short papers.

Please refer to the symposium web page for updated information.

Full paper submissions:  May 14th, 2021

Notification:        July 16th, 2021

Camera-ready and author's registration: July 30th, 2021

General co­-Chairs 

Mihalis Psarakis, University of Piraeus, GR 

Prashant Joshi,  INTEL, USA 

Program co­-Chairs

Luigi  Dilillo, LIRMM, FR 

Luca Cassano, Politecnico di Milano, IT