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1st IEEE Federative Event on Design for Robustness
CALL FOR PARTICIPATION
Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications.
The IEEE Federative Event on Design for Robustness (FEDfRo) brings together:
FEDfRo 2016 will be held at Sant Feliu de Guixols, Costa Brava, Spain.
The area offers a brilliant experience, with so much to offer: a beautiful natural setting, culture, leisure, sport, and a delightful seafront location with a multitude of idyllic small coves and longer bays with fine and golden sand …
Sant Feliu de Guixols has also an impressive monumental site, formed by the parish church and different elements from the Romanesque monastery of the village, with its famous Porta Ferrada.
FEDFRo 2016 will be held at the hotel Eden Roc, located at a 1 km from Sant Feliu de Guixols, and 8 minutes walking distance from the main golden sandy beach of the town. Eden Roc is built on the seafront rocks of a unique and quiet peninsula, enjoying stunning sea views, and is situated at few meters from the seafront, with its nice terraces, gardens, and swimming pools touching the sea.
For more information, visit us on the web at: http://tima.imag.fr/conferences/fedfro/fedfro16/
The 1st IEEE Federative Event on Design for Robustness is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
IEEE DESIGN & TEST EIC
ASIA & PACIFIC
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