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IEEE Transactions on Emerging Topics in Computing 

Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems 

http://bit.do/eQwx5

CALL FOR PAPERS

About

IEEE Transactions on Emerging Topics in Computing (TETC) seeks original manuscripts for a Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in future VLSI systems. 

This special session is a follow up of the IEEE VLSI Test Symposium 2019 addressing the main topics discussed during the conference. All aspects of design, manufacturing, test, monitoring and securing of systems affected by defects and malicious attacks are of interest. The relevant topics for this special section include, but are not limited to:

  • Yield Analysis and Modeling: Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
  • Error Detection, Correction, and Recovery: Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques, architectural-specific techniques, system-level strategies.
  • Cross-layer Dependability Analysis and Validation: fault injection techniques; dependability characterization; aging modeling and analysis with emphasis on cross-layer solutions.
  • Defect and Fault Tolerance: Reliable circuit/system synthesis; radiation hardened and/or tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors; aging management and recovery strategies.
  • Safe design for critical applications: methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
  • Design for Security: fault attacks, fault tolerance-based counter-measures, Scan-based attacks and counter-measures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and reliability.
  • Reliable and secure systems design with emerging computing paradigms: Reliable and secure design techniques for emerging computing paradigms (e.g., approximate computing, neuromorphic computing, in-memory computing).

Submissions 

Submitted papers must include a new significant research-based technical contribution. The submitted papers must include a clear evaluation of the proposed solutions (based on simulation and/or implementations results) and comparisons to state-of-the-art solutions.

Extended versions of published conference papers are welcome but there must be at least 40% of new impacting technical/scientific material in the submitted manuscript. As an author, you are responsible for understanding and adhering to the submission guidelines.  Please thoroughly read these before submitting your manuscript. 

Please submit your paper to Manuscript Central at https://mc.manuscriptcentral.com/tetc-cs.

While submitting through ScholarOne, please select the option “Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems.”

Key Dates

Deadline for submissions: July 1, 2019
First decision (accept/reject/revise expected): September 2, 2019
Submission of revised papers: October 1, 2019
Notification of final decision (expected): December 13, 2019

Additional Information

Guest editors:

Stefano Di Carlo (Politecnico di Torino, Italy)
Peilin Song (IBM Research, New York, NY, USA)
Alessandro Savino (Politecnico di Torino, Italy)

Corresponding TETC editor:
Weiqiang Liu (NUAA, Nanjing, China)

For additional information please send an email to tetc.sivlsitest@gmail.com. Papers under review elsewhere are not acceptable for submission.
For more information, visit us on the web at: http://bit.do/eQwx5
This special issue is linked with the 37th IEEE VLSI Test Symposium 2019 that is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

IEEE Computer Society-Test Technology Technical Council

TTTC CHAIR
Chen-Huan CHIANG
Intel - USA
E-mail chen-huan.chiang@intel.com

PAST CHAIR
Michael NICOLAIDIS
TIMA laboratory - France
E-mail michael.nicolaidis@imag.fr

TTTC 1ST VICE CHAIR
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
E-mail figueras@eel.upc.es

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Adith SINGH
Auburn University – USA
E-mail adsingh@eng.auburn.edu

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys, Inc. – USA
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com


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