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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
CALL FOR PAPERS
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in digital systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The topics include (but are not limited to) the following ones:
1. Yield Analysis and Modeling: Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.
2. Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
3. Design For Testability in IC Design: FPGA, SoC, NoC, ASIC, microprocessors.
4. Error Detection, Correction, and Recovery Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.
5. Dependability Analysis and Validation: Fault injection techniques and environments; dependability characterization.
6. Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing.
7. Defect and Fault Tolerance: Reliable circuit/system synthesis; radiation hardened/tolerant processes and design; design space exploration for dependable systems, transient/soft faults and errors.
8. Totally Fail-Safe Design for Critical Applications: Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
9. Emerging Technologies: Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
10. Hardware security: Fault attacks, fault tolerance-based countermeasures, Scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.
Prospective authors are invited to submit original and unpublished contributions.
Two types of submissions are possible: (i) regular papers (6 pages - with the opportunity to purchase 2 additional ones), and (ii) short papers (4 pages) to be presented as posters. Both types will be included in the symposium proceedings and should adhere to the IEEE conference template, 2-columns style (available on conference web site), and submitted as PDF file, electronically.
Please refer to the symposium web page for updated information (www.dfts.org),
We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page max) of the proposed panel.
Submission deadline: May 8, 2015
Acceptance notification: July 6, 2015
Camera ready deadline: August 7, 2015
Industrial liasons chairs:
For more information, visit us on the web at: http://www.dfts.org
The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
ITC GENERAL CHAIR
TEST WEEK COORDINATOR
TUTORIALS AND EDUCATION
MIDDLE EAST & AFRICA
PRESIDENT OF BOARD
SENIOR PAST CHAIR
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC
ASIA & PACIFIC
INDUSTRY ADVISORY BOARD