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5th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
CALL FOR PAPERS
The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), microbumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
Topic Areas � You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop�s areas of interest include (but are not limited to) the following topics:
Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop�s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.
It is also not yet too late to sign up with your company for (1) a table-top demo and/or (2) corporate support.
The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc.
Submission deadline: September 17, 2014 (EXTENDED)
Notification of acceptance: September 22, 2014
Camera-ready material: October 6, 2014
Yervant Zorian � General Chair
700 East Middlefield Road
Mountain View, CA 94043-4033, USA
Tel.: +1 (650) 584-7120
Erik Jan Marinissen � Program Chair
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Finance Vice-Chair / Arrangements:
Program Committee Members:
For more information, visit us on the web at: http://3dtest.tttc-events.org
3D-TEST'15 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 1ST VICE CHAIR
ITC GENERAL CHAIR
TEST WEEK COORDINATOR
TUTORIALS AND EDUCATION
MIDDLE EAST & AFRICA
PRESIDENT OF BOARD
SENIOR PAST CHAIR
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC
ASIA & PACIFIC
INDUSTRY ADVISORY BOARD