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IEEE International Symposium on Defect and Fault Tolerance
CALL FOR PARTICIPATION
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field.
All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The symposium is held yearly, around the world, and this year will be located in Austin, Texas, U.S.A.
Advance Discount Registration Deadline: September 16th, 2012!
Maps and directions to reach the venue can be found here.
There is no preferred hotel where to stay among the several in the area.
Conference registration now open on the website.
|Preliminary technical program now available link.|
For more information on general aspects and location matters, please contact the general co-chairs:
For more information on general aspects and location matters, please contact the technical program co-chairs:
Prashant D. Joshi (Intel,USA)
Massimo Violante (Politecnico di Torino, Italy)
For more information, visit us on the web at: http://www.dfts.org/
The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
1ST VICE CHAIR
ITC GENERAL CHAIR
EAST & AFRICA
PRESIDENT OF BOARD
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC