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IEEE Defect and Data-Driven Testing
(D3T 2010)

November 4-5, 2010
Austin, TX, USA

http://d3t.tttc-events.org/

Advance Registration Deadline October 1st, 2010!
CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- Committees

Scope

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As technology scales, various new types of defects are presenting unique challenges to the test community. New test defect and data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-50nm technology nodes and their impact on product quality and in-field reliability. Defect and data-driven testing (D3T) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in production test. D3T uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. D3T can provide the basis for Adaptive Test decisions on which test conditions, tests, or test subsets to add/remove. It can be utilized for improving the overall quality of test by the use of outlier analysis. However, how to implement and analyze test and defect data in making these decisions is not a widely understood or utilized process in the industry. Closing the gap on knowledge of the process, new test techniques, and how defect models are being used to adapt test flows will be the goals of this year’s D3T workshop.

Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

  • Outlier Identification
  • Data-Driven Testing (DDT)
  • Test Data Analysis
  • Yield Learning and Analysis Using DDT
  • Adaptive Test
  • Data-Mining Methods for Test Data Processing
  • Low Voltage Testing
  • Elevated Voltage Testing and Stress Testing
  • Reliability and Yield
  • Nanometer Test Challenges
  • Defect Coverage & Metrics
  • Mixed Current/Voltage Testing
  • Economics of Defect Based Testing
  • Fault Localization & Diagnosis
  • Noise and Crosstalk Testing
  • Transition and Delay Fault Testing
Key Dates
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Advance Registration Deadline: October 1st, 2010!
The Venue
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The ITC conference and all associated Test Week events will be held at the Austin Convention Center, Austin, Texas. Austin is the capital of the state of Texas, and its 1888 capitol building is an interesting landmark. Also of interest are the main campus of The University of Texas and the Lyndon B. Johnson Library and Museum. Close to the convention center is the lively East Sixth Street entertainment district which features many restaurants and a variety of music in the ―Live Music Capital of the World‖. The downtown area has miles of waterfront trails suitable for walking and jogging and is also home to the largest urban bat population in the US whose spectacular flight can be observed just before sunset. For more information about Austin, visit http://www.austintexas.org. Lodging for Test Week is in several hotels in the vicinity of the convention center.
Workshop Registration
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On-line Registration

Advance Program
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Thursday -- Friday

November 4, 2010 (Thursday)
 
4:00 PM - 5:00 PM OPENING SESSION
4:00 - 4:15

Opening Remarks
Al Crouch (Asset Intertech, USA), General Chair D3T
Sankaran Menon (Intel Corporation, USA), Program Chair D3T

4:15 - 5:00

Thursday Keynote: Adaptive Test Flows, is the naturally occurring test data enough?
Robert Daasch (University of Portland, USA)

 
5:00 PM - 6:30 PM Session 1 - Test Standards Session
Al Crouch (Asset Intertech, USA)
5:00 - 5:30

IEEE P1687 and 3D-Die Standards
Al Crouch (Asset Intertech, USA)

5:30 - 6:00
Standards-based, Tester independent Tool for Silicon Diagnosis and Volume Yield Improvement
Jack Frost (Teseda Corp., USA)
6:00 - 6:30
XATF eXtendible Adaptive Test Format
Stefan Eichenberber (NXP Semiconductors, The Netherlands)
 
7:00 PM - 9:00 PM WORKSHOP WELCOME RECEPTION
 
November 5, 2010 (Friday)
 
8:00 AM - 8:45 AM FRIDAY KEYNOTE
 

State of Adaptive Testing Today
Taylor Scanlon (Pintail Technologies, USA)

 
8:45 AM - 10:30 AM Session 2: Invited Talks on Adaptive Testing and Test Data Mining
8:45 - 9:20

Adapting to Adaptive Testing
Adit Singh (Auburn University, USA)

9:20 - 9:55
Adaptive Testing
Jeff Roehr (MediaTek, USA)
9:55 - 10:30
Data Mining and Machine Learning With Applications to Test, Verification, and Validation
Li-C Wang (University of California, Santa Barbara, USA)
 
10:30 AM - 10:50 PM COFFEE BREAK
 
10:50 AM - 11:50 AM Session 3: Yield Improvement
Session Chair: Sankaran Menon, (Intel Corporation, USA)
10:50 - 11:20

A Change in Methodology Accelerates the Isolation in Root Cause of Defects for Improving Yield and Lowering Costs
Ralph Sanchez (Teseda Corp., USA)

11:20 -11:50
How To Maximize Outlier Detection While Minimizing Yield Loss Through A Unique Application Of Statistical PAT, Dynamic PAT, Geographical PAT, And Other Maverick Elimination Techniques In An Automated Production Environment
Wesley Smith (Galaxy Corporateion, USA)
 
11:50 AM - 1:00 PM LUNCH
 
1:00 PM - 2:10 PM Session 4: Testability, Test Compression and Intermittent Faults
Session Chair: Nisar A
hmed (Texas Instruments, USA)
1:00 - 1:30

Applying K Longest Path Per Gate (KLPG) Tests to a Microprocessor - Invited Talk
Hank Walker (Texas A&M University, USA)

1:30 - 1:50
Low-Capture-Power Post-Processing Test Vectors For Test Compression Using SAT Solver
Kohei Miyase (Kyushu Institute of Technology, Japan)
1:50 - 2:10

Emphasis On The Existence Of Intermittent Faults In Embedded Systems
Julien Guilhemsang (CEA, LIST, CEDEX, France)

 
2:10 PM - 2:30 PM COFFEE BREAK
 
2:30 PM - 4:00 PM Panel Discussion - Challenges of Adaptive Testing
 

Organizers:

Jeff Roehr (MediaTek, USA)
Sankaran Menon (Intel Corp., USA)

Moderator:

Jeff Roehr (MediaTek, USA)

Panelists:

Adit Singh (Auburn University, USA)
Stefan Eichenberber (NXP Semiconductors, The Netherlands)

Wes Smith (Galaxy Corporation, USA)

 
Committees
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Organizing Committee

General Chair
Al Crouch, Asset-Intertech

Program Chair
Sankaran M. Menon, Intel

Co-Program Chair
Jeff Roehr, Mediatek

Vice Program Chair
Nisar Ahmed, TI

Finance Chair
Sankaran M. Menon, Intel

Publicity Chair
Arani Sinha, AMD

Publication Chair
Chintan Patel, UMBC

Steering Committee

Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Start Test
Jim Plusquellic, U. New Mexico
 

Program Committee

Rob Aitken, ARM
Tom Bartenstein, Cadence
Nemat Bidokhti, Cisco
Ken Butler, TI
Krish Chakrabarty, Duke Univ.
Sreejit Chakravarty, LSI Logic
John Carulli, TI
Bruce Cory, Nvidia
Jennifer Dworak, Brown University
Patrick Girard, LIRRM
Sandeep Goel, TSMC
Rohit Kapur, Synopsys
Ajay Koche, Consultant
Mike Laisne, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Teresa McLaurin, ARM
Amit Nahar, TI
Suriyaprakash Natarajan, Intel  
Jay Orbon, Verigy
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Mani Soma, U Washington
Claude Thibeault, Ecole Tech
Li C. Wang, UCSB              
Xiaoqing Wen, Kyushu Institute of Tech.
LeRoy Winemberg, Freescale
Qiang Xu, CUHK

Mahmut Yilmaz, AMD

For more information, visit us on the web at: http://d3t.tttc-events.org/

The IEEE Defect and Data-Driven Testing (D3T 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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