3D-Test 2010 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

The new 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

Topic Areas – You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:

Defects due to Wafer Thinning
Defects in Intra-Stack Interconnects
DfT Architectures for 3D-SICs
EDA Design-to-Test Flow for 3D-SICs
Failure Analysis for 3D-SICs
Known-Good Die / Stack Testing
Pre-Bond and Post-Bond Testing
Reliability of 3D-SICs

Standardization for 3D Testing
System/Board Test Issues for 3D-SICs
Test Cost Modeling for 3D-SICs
Test Flow Optimization for 3D-SICs
Tester Architecture incl. ATE and BIST
Thermal/Mechanical Stress in 3D-SICs
TSV Test, Redundancy, and Repair
Wafer Probing and Probe Damage of 3D-SICs

Submissions

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Submission Instructions – Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.

Publications – The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. Authors of a selected subset of papers will be invited to submit extended journal versions of their manuscripts to be considered for a Special Issue of Springer’s ‘Journal of Electronic Testing – Theory and Applications’ (JETTA) being planned for 2011.

Key Dates

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Submission deadline: August 23, 2010
Notification of acceptance: October 1, 2010
Final copy deadline: October 22, 2010

Additional Information

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Yervant Zorian – General Chair
Virage Logic
47100 Bayside Parkway
Fremont, CA 94538, USA
Tel.: +1 (510) 360-8035
Fax: +1 (510) 360-8078
E-mail: yervant.zorian@viragelogic.com

Erik Jan Marinissen – Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
E-mail: erik.jan.marinissen@imec.be

Committees

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General Chair:
Y. Zorian – Virage Logic (US)

Program Chair:
E.J. Marinissen – IMEC (B)

Finance Chair:
Said Hamdioui – TU Delft (NL)

Publication Chair:
M. Grosso – Politecnico di Torino (I)

Publicity Chair:
F. von Trapp – 3DInCites (US)

Web Chair:
G. Jervan – Tallinn Univ. of Techn. (EE)

Program Committee Members:
S. Adham – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
S. Bhatia – Oasys (US)
C. Bullock – Texas Instruments (US)
E. Cormack – DfT Solutions (UK)
K. Chakrabarty – Duke Univ. (US)
S. Chakravarty – LSI (US)
V. Chickermane – Cadence (US)
A. Crouch – Asset Intertech (US)
T. Eaton – Cisco Systems (US)
G. Fleeman – Advantest (US)
M.-L. Flottes – LIRMM (F)
P. Franzon – NC State Univ. (US)
S.-Y. Huang – NTHU (TW)
M. Higgins – Analog Devices (IRL)
R. Kapur – Synopsys (US)
M. Knox – IBM (US)
P. Lebourg – ST Microelectronics (F)
S. Lecomte – ST-Ericsson (F)
D. Lefever – Advantest (US)
M. Laisne – Qualcomm (US)
H.-H. Lee – Georgia Tech (US)
I. Loi – Universita di Bologna (I)
M. Loranger – FormFactor (US)
T. McLaurin – ARM (US)
N. Minas – IMEC (B)
W. Moorhead – Scanimetrics (CAN)
K. Parker – Agilent Technologies (US)
S. Pateras – Mentor Graphics (US)
B. Patti – Tezzaron Semiconductor (US)
F. Pöhl – Infineon Technologies (D)
M. Ricchetti – AMD (US)
D. Rishavy – TEL Test Systems (US)
T. Thärigen – Cascade Microtech (D)
E. Volkerink – Verigy (US)
L. Whetsel – Texas Instruments (US)
Y. Xie – Penn. State Univ. (US)
Q. Xu – Chinese Univ. Hong Kong (HK)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test10) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).