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25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CALL FOR PAPERS
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The topics include (but are not limited to) the following ones:
Prospective authors should prepare an extended summary or the full paper (up to 9 pages in the IEEE 6X9 single column format), to be submitted as PDF file. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:
We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.
Paper Publication and Author Registration: Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library. Each accepted paper MUST have at least an author with a paid full registration for the manuscript to be included and published in the proceedings; an author is also expected to attend and present the paper at the Symposium.
Journal Special Issue: There is a possibility for inviting the authors of selected papers presented at DFT 2010 to submit an extended version of their work in a special issue of an archival journal.
Submission deadline: May 3, 2010
For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.
Local Arrangements Co-chairs
P. Ampadu, University of Rochester
C. Bolchini, Politecnico di Milano
S. Chakravarty, LSI Logic
Y. Choi, Hongik University
M. Favalli, University of Ferrara
J. Figueras, Univ. Polit. Catalunya
M. Fukushi, Tohoku University
D. Gizopoulos, University of Piraeus
S. Hamdioui, Delft University of Technology
C. Huang, Nat'l Tsing Hua U.
A. Jas, Intel
N. Jha, Princeton
W. Jone, University of Cincinnati
Y. Kim, Northeastern University
I. Koren, UMASS Amherst
R. Leveugle, TIMA labs
F. Lombardi, Northeastern University
Y. Makris, Yale
I. Markov, University of Michigan
C. Metra, University of Bologna
M. Nakanishi, NTT
Z. Navabi, Worcester Polytechnic Institute
N. Nicolici, McMaster University
M. Ottavi, University of Rome "Tor Vergata"
N. Park, Oklahoma State University
A. Paschalis, University of Athens
Z. Peng, Linkoping University
W. Pleskacz, Warsaw U.T.
S. Pontarelli, University of Rome "Tor Vergata"
J. Prashant, Intel
M. Rebaudengo, Politecnico di Torino
S. Reddy, University of Iowa
A. Salsano, University of Rome "Tor Vergata"
D. Sciuto, Politecnico di Milano
M. Tehranipoor, University of Connecticut
J. Teixeira, INESC-ID Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, University of Texas at Austin
R. Velazco, TIMA labs
M. Violante, Politecnico di Torino
L. Wang, University of Connecticut
X. Wen, Kyushu Institute of Technology
Y. Yoshioka, Hirosaki University
For more information, visit us on the web at: http://www.dfts.org
The 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
1ST VICE CHAIR
ITC GENERAL CHAIR
EAST & AFRICA
PRESIDENT OF BOARD
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC
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