TTTC's Electronic Broadcasting Service
1st IEEE International Workshop on
Held in conjunction with Test Week (International Test Conference 2009)
CALL FOR PAPERS
In IC designs today, analog content is no longer a small portion of silicon as it was in the past. With various interfaces such as PCIe, DDR, Display-IO, HT, and other components such as PLLs, DACs, Temperature Sensors, the proportion of silicon die area covered by analog circuits is continually increasing with each design generation. Starting with 65nm process technology, a growing market need for high speeds, large bandwidths and small geometries have made designs a lot more complex in terms of testability and manufacturability. Majority of test for analog portions of a chip have been marginalized to characterization on the ATE and boards. This characterization is often planned around various electrical and thermal corners and the outcome is heavily dependent on process technology. More often than not, rigorous testing of the full range of properties of an analog circuit is neglected during production-ramp and production. Prime among the many reasons for this lack of rigor in test of analog circuits is overall test cost.
In this workshop, we will bring to fore, various issues associated with test and validation of high speed analog circuits, including innovative solutions for high parametric coverage and lower test cost. The scope of the workshop includes:
To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (500 words) or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.
Submit a copy of your paper proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than October 14th, 2009.
Submit your paper proposal to:
Authors will be notified of the disposition of their papers by October 16th, 2009.
Submission deadline: October 14th, 2009
Vice General Chair
The1st IEEE International Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
1ST VICE CHAIR
ITC GENERAL CHAIR
EAST & AFRICA
PRESIDENT OF BOARD
TTTC 2ND VICE CHAIR
IEEE DESIGN & TEST EIC
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