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Test Track at the
Design, Automation and Test in Europe Conference and Exhibition (DATE 2010)

March 8-12, 2010
Dresden, Germany

http://www.date-conference.com/

CALL FOR PAPERS
Scope -- Test Topic Areas -- Submissions -- Key Dates -- Additional Information

Scope

The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together design automation researchers, users and vendors, as well as specialists in the design, test, and manufacturing of electronic systems and circuits. One of the tracks of DATE is devoted to Methods, Tools and Innovative Experiences in Testing Electronic Circuits and Systems. You are invited to submit your research contributions to the test track.

This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops, as well as a Designers’ Forum. The DATE conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information.

Test Topic Areas
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The test track is organised in six topics. These topics together with their chairs and area descriptions are given as follows.

T1 System and Industrial Test
Chairs: Erik Jan Marinissen, IMEC, Belgium; Peter Harrod, ARM Ltd, UK
Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor-based test; infrastructure IP;  industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

T2 Design for Test and BIST
Chairs: Krishnendu Chakrabarty, Duke Univ., USA; Sandeep Kumar Goel, USA
Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, Dft economics.

T3 Test Generation, Simulation and Diagnosis
Chairs: Nicola Nicolici, McMaster University, Canada; Bart Vermeulen, NXP, The Netherlands
Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

T4 On-Line Testing and Fault Tolerance
Chairs: Dimitris Gizopoulos, University of Piraeus, Greece; Davide Appello, STMicroelectronics, Italy
Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependability evaluation, dependable system design; redundant systems design; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications.

T5 Test for Variability, Reliability and Defects
Chairs: Sandip Kundu, Massachusetts Univ., USA; Rob Aitken, ARM, USA
Identification, characterization and modeling of defects, faults and degradation mechanisms; Defect based fault analysis, Simulation and ATPG of defect based faults; Reliability analysis and modeling techniques, FMEA and Physics of failure; Test for noise and uncertainty; Design for Reliability and Design for Variability and their impact on test; Test and reliability of redundant systems; Test and reliability issues in the presence of leakage; Challenges of ultra low-power design on test and reliability; Modeling and test techniques for physical sources of errors such as process, voltage and temperature variations; Error-resilient nano design systems.

T6 Analog, Mixed-Signal, RF and Mixed-Technology Test
Chairs: Hans Kerkhoff, University of Twente, The Netherlands; Abhijit Chatterjee, Georgia Institute of Technology, USA
Test techniques for mixed-signal, RF and multi-GHz electronics; Test techniques for embedded MEMS/bioMEMS/MOEMS sensors and actuators; assembly engineering for SiP/SoC/SoP/PoP; Failure modelling and analysis techniques; Defect characterization and fault modelling; Fault simulation and test generation algorithms; DfT/DfM/DfY/DfR (DfX) techniques; BIST; Test coverage metrics and statistical modeling; Effective defect screening techniques; Diagnosis and self-repair.

Submissions

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All manuscripts must be submitted electronically before September 6th, 2009, following the instructions on the conference Web page:

www.date-conference.com

The accepted file format is PDF Manuscripts received in hard-copy form will not be processed.

Papers can be submitted for either standard oral presentation or for interactive presentation. Standard oral presentations require novel and complete research work supported by experimental results, and are held in front of a full audience. Besides these, DATE will again include interactive presentations of novel ideas that may require additional research or lack experimental data. Presentations are given on a laptop in a face-to-face discussion area.

Submissions should not exceed 6 pages in length for oral-presentation and 4 pages in length for interactive-presentation papers, and should be formatted as close as possible to the final format: A4 or letter sheets, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience). To permit blind review, submissions should not include the author names.  Any submission not in line with the above rules will be discarded.

All papers will be evaluated with regard to their suitability for the conference, originality and technical soundness. The Programme Committee reserves the right to accept interesting contributions that do not meet the criteria for standard oral presentations, as interactive presentations.

Key Dates

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Submission deadline: September 6, 2009

Additional Information
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Patrick Girard - DATE Test & DfM Chair
LIRMM
University of Montpellier / CNRS
34392 Montpellier, France
e-mail: girard@lirmm.fr

Wolfgang Mueller - DATE Program Chair
Paderborn University
C-LAB, Fuerstenallee 11,
D-33098 Paderborn, Germany 
e-mail: wolfgang@acm.org

For more information, visit us on the web at: http://www.date-conference.com/

The Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel.
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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