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IEEE International High-Level Design, Validation and Test Workshop
(HLDVT 2009)

Nov. 4-6, 2009
Grand Hyatt
San Francisco, California, USA

http://www.hldvt.com/09


CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

HLDVT 2009 is the fourteenth in a series of annual workshops designed to bring together a community of researchers in the areas of design, validation, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum in recent years for researchers and practitioners to discuss the practical issues associated with simulation and validation of extremely large designs. For detailed information, please visit http://www.hldvt.com/09/.

The topics of interest include (but not limited to):

Simulation-Based Validation
Formal Verification
Specification-based Design and Validation
Error Trace Analysis and Debug
Hybrid SAT/BDD/ATPG Methods
On-Chip and Core-Based Testing
Coverage-driven Test Generation
Design/Synthesis for Test
Hardware/Software Co-Validation
Prototyping and Emulation
Post-silicon Validation and Debug

Submissions

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The Program Committee invites authors to submit papers not to exceed 8 pages (10pt minimum font size with reasonable margins and line spacing) describing original and unpublished work. Proposals for panels and special sessions are also invited. All submissions must be made electronically in PDF format using the paper submission webpage: http://www.hldvt.com/submissions

Submission deadline: June 12, 2009 (notification: August 10)
Final manuscript due: September 07, 2009

Authors of selected HLDVT'09 papers will be invited to submit extended versions for a special issue of Springer Journal of Electronic Testing, to be published in 2010.

During paper submission the authors must commit to register and attend the workshop to present the paper if it is accepted. Every accepted paper must have at least one of the authors pre-registered for the workshop during submission of camera-ready version to ensure that the paper appears in the final program and conference proceedings. IEEE reserves the right to exclude a paper from distribution after the workshop (e.g., removal from IEEE Xplore) if the paper is not presented at the workshop.

Key Dates

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Submission deadline: June 12, 2009
Notification of acceptance: August 10, 2009
Final copy deadline: September 07, 2009

Additional Information
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Questions regarding paper submissions and the program may be addressed to the program chair: Prabhat Mishra, programchair@hldvt.com.

Other questions may be addressed to the general chair: Priyank Kalla, generalchair@hldvt.com.

Committees
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Organizing Committee

General Chair
Priyank Kalla, University of Utah

Program Chair
Prabhat Mishra, University of Florida

Past Chair
Prab Varma, Blue Pearl Software

Finance Chair
Zeljko Zilic, McGill University

Publications Chair
Miroslav Velev, Aries Design Automation

Web Publicity Chair
Ismet Bayraktaroglu, Sun

Publicity Chair
Shireesh Verma, Conexant

Local Arrangements Chair
Kiran Ramineni, Marvell Semiconductor

Program Committee

Mark Aagaard, University of Waterloo
Jacob Abraham, UT Austin
Valeria Bertacco, University of Michigan
Pankaj Chauhan, Calypto
Tim Cheng, UC Santa Barbara
Franco Fummi, University di Verona
Malay Ganai, NEC Labs
Eric Hennenhoefer, Obsidian Software
Ian Harris, UC Irvine
John Hayes, University of Michigan
Michael Hsiao, Virginia Tech
Alan Hu, University of British Columbia
Torsten Schober, IBM
Jai Kumar, Sun
Priyadarsan Patra, Intel
Wolfgang Rosenstiel, T¨ubingen Univ.
Pablo Sanchez, University of Cantabria
Sandeep Shukla, Virginia Tech
Wei Qin, Boston University
Li-C. Wang, UC Santa Barbara
Hao Zheng, University of South Florida
Avi Ziv, IBM

Steering Committee

Bernard Courtois, CMP-TIMA
Sujit Dey, UC San Diego
Masahiro Fujita, University of Tokyo
Prab Varma, Blue Pearl Software

For more information, visit us on the web at: http://www.hldvt.com/09

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel.
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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