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27th IEEE VLSI TEST SYMPOSIUM (VTS 2009)
May 3rd May 7th, 2009
Seascape Beach Resort, Santa Cruz California, USA

http://www.tttc-vts.org

Advance Registration Deadline Extended to April 24th!
CALL FOR PARTICIPATION


REGISTRATION IS NOW AVAILABLE ONLINE
Advance Registration Rates End April 24, 2009

Program Highlights -- More Information -- Committees

Program Highlights

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world's leading test experts and professionals from both industry and academia join to present and debate key issues in testing. VTS 2009 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Panels, New Topic Sessions, Full-day Tutorials, co-located Workshops, and the Innovative Practices Track.

PLENARY SESSION

Keynote: John Kibarian, CEO and President of PDF

Invited Keynote: Bozena Kaminska, Canadian Research Chair, Simon Fraser Univ., Canada

TECHNICAL PAPER SESSIONS will present the latest research results in test, including:

  • Microprocessor Test
  • Fault Models
  • Robust Design and Fault Tolerance
  • Delay Fault Testing
  • Silicon Debug and Diagnosis
  • Signal Integrity and Power Supply Noise
  • Yield
  • Test and Verification
  • Transistor Aging
  • Test Compaction and BIST
  • Test and Radiation Test
  • Analog Test and Calibration
  • Emergent Technology and Security

INNOVATIVE PRACTICES (IP) TRACK highlights cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them.

  • Design and Test Practices and Trends in East Asia
  • ATE Vision 2020: New frontiers for ATEs
  • Industrial Approaches for Quality and Compression
  • Yield and Marginalities
  • New Practices in Defect-based Testing
  • Value of DFM in Volume Diagnosis Arena
  • DFT and Test Practices for Power-Managed Low Power Chips
  • Test Practices for High Speed I/O

SPECIAL SESSIONS will include:

  • EMBEDDED TUTORIAL: Quantum Wires and Quantum Wire Arrays
  • NEW TOPICS: At-Speed Testing in the Face of Process Variations; Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips
  • PANELS: Apprentice – VTS Edition: Season 2; DFT and Test Problems from the Trenches; Analog Test and Characterization: The Long Road To Realization; SoC Power Management Implications on Validation and Testing
  • TTTC 2009 Best Doctoral Thesis Contest
  • Student Posters

FULL-DAY TUTORIALS and WORKSHOPS complement the core technical program of VTS.

WORKSHOPS

IEEE Workshop on Test of Wireless Circuits and Systems (WTW)

TEST TECHNOLOGY EDUCATIONAL PROGRAM (TTEP) TUTORIALS

  • Advanced Topics and Recent Advances in Silicon Debug and Diagnosis
  • Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability

The social program at VTS provides an opportunity for informal technical discussions among participants. This year, the social program will feature a visit to a local winery (transportation provided) and a banquet sunset dinner on the beach. Santa Cruz, California provides a very attractive backdrop for all VTS 2009 activities. We are sure that you will find VTS 2009 enlightening, thought-provoking, rewarding, and enjoyable!

More Information

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General Information

General Chair
Magdy Abadir
Freescale Semiconductors
M.Abadir@freescale.com

Submission Related Information

Program Chair
Cecilia Metra
ARCES – University of Bologna
cecilia.metra@unibo.it


Committees

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General Chair
M. Abadir - Freescale

Program Chair
C. Metra – U of Bologna

Past Chair
A. Orailoglu - UC San Diego

Vice-General Chair
P. Maxwell - Micron

Vice-Program Chair
M. Renovell – LIRMM

New Topics
B. Courtois – TIMA

Special Sessions
L. Anghel – TIMA
C.P. Ravikumar – Texas Instruments

Innovative Practices Track
K. Hatayama – STARC
S. Mitra – Stanford U

Registration
C. Thibeault–E Tech Sup Montreal
S. Ozev - Arizona

Publicity Chair
S. Ravi – Texas Instruments

Publicity Members
I. Bayraktaroglu - Sun
S. Di Carlo - Politecnico di Torino
G. DI Natale - LIRMM

Finance
C.H. Chiang - Alcatel-Lucent

Local Arrangements
L. Wang  - UCSB

Publications
Y. Makris - Yale

Audio/Visual
S. Hellebrand – U Paderborn

Regional Liaisons
V. Champac -  Mexico
B. Cory - Nvidia
R. Makki– UAE U
Y. Sato – Hitachi
Hahanov - Ukrain
Z. Peng – Linkoping U

Ex-Officio
Y. Zorian – Virage Logic

Program Committee
J. Abraham– U of Texas Austin
V. Agrawal – Auburn U
D. Appello – ST Microelectronics
K. Arabi – Qualcomm
B. Becker – U Freiburg
J. Bhadra – Freescale
L. Carro - UFRGS
C.J. Clark – Intellitech
R. Galivanche – Intel
P. Girard - LIRMM
D. Gizopoulos – U Piraeus
X. Gu – Cisco
S. Gupta – U of Southern California
I. Harris - U C Irvine
I. Hartanto – Xilinx
B. Kaminska – Pultronics
R. Kapur - Synopsys
A. Khoche – Verigy
H. Konuk – Broadcom
X. Li – Chinese Acad. Sci.
F. Lombardi – Northeastern U
M. Lubaszewski - UFRGS
E.J. Marinissen– IMEC
S. Mourad – Santa Clara U
P. Muhmenthaler– Infineon
Z. Navabi – Worcester Polytechnic
J. Plusquellic – UMBC
A. Raghunathan – Purdue U
J. Rajski – Mentor Graphics
S. Reddy – U. Iowa
R. Segers – NXP
J. Segura – U Illes Balears
S. Shoukourian – Virage Logic
M. Soma – U of Washington
S. Sunter LogicVision
J. Tyszer – Poznan U
R. Ubar – Tallin U.
C. -W. Wu – Nat Tsing Hua U
H.-J Wunderlich – U. Stuttgart

Steering Committee
J. Figueras – U Pol Catalunya
A. Ivanov – U of British Columbia
M. Nicolaidis – TIMA
P. Prinetto – Polit di Torino
A. Singh – Auburn U
P. Varma – Blue Pearl
Y. Zorian – Virage Logic

For more information, visit us on the web at: http://www.tttc-vts.org

The 27th IEEE VLSI TEST SYMPOSIUM (VTS 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel.
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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