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15th International Test Synthesis Workshop (ITSW 2008)
April 7-9, 2008
Santa Barbara, California, USA

http://www.tttc-itsw.org

CALL FOR PARTICIPATION
Scope -- Advance Program -- Committees

Scope

Theme: At-Speed Scan: Challenges and Opportunities

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.

This year’s workshop will focus on at-speed scan tests, looking at various issues like hardware support, yield loss, test power, defect coverage, pseudo-functional tests and explore whether it is possible to replace functional delay tests with at-speed scan and still maintain product quality. As always, ITSW is open to all submissions in the area of test, including, but not limited, to the following:
  • Register Transfer Level DFT
  • High-Level/Behavioral Test Synthesis
  • System-on-a-Chip (SoC) DFT
  • Memory and Logic BIST
  • Test Synthesis for Debug and Diagnosis
  • DFT for Mixed-Signal Circuits
  • Test Resource Partitioning
  • Functional Verification
  • Power and Noise-Aware Test
  • Design for Reliability
  • High-speed I/O test
  • Reducing the Cost of Test
  • Design for Manufacturing and Yield
  • Board and System Test
  • SER / Concurrent Error Detection
  • Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org

Advance Program

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Monday -- Tuesday -- Wednesday

April 7, 2008 (Monday)
 
7:30 - 8:15 AM CONTINENTAL BREAKFAST
 
8:15 - 9:15 AM Opening Session
8:15 - 8:30
Opening Message
Nilanjan Mukherjee, General Chair
8:30 - 9:15
Keynote Address
TBD
 
9:15 - 10:15 AM Opening Session
9:15 - 9:45
Reducing the Cost of Test – An Adaptive Test Solution
R. Turakhia, M. Ward (LSI)
9:45 - 10:15
Efficient Production Test Selection and Ordering based on Functional Fault Grading
J.H. Jeong, D. Mahon, M. Laisne, A. Ambler
 
10:15 - 10:45 AM COFFEE BREAK
   
10:45 - 12:15 PM DFT
Chair: C. Dixit, LSI
10:45 - 11:15
Strategies for Power-Aware DFT
V. Chickermane, P. Gallagher, K. Chakravadhanula (Cadence)
11:15 - 11:45
Clock Gating to Improve At-Speed Scan
D. Dehnert (Intel)
11:45 - 12:15
Update: the P1687 (IJAG) Hardware Proposal for Efficient Embedded Instrument Access, Bandwidth, and Connectivity
A. Crouch, J. Rearick, K. Posse
 
12:15 - 1:30 PM LUNCH
 
1:30 - 3:30 PM Test Generation and Diagnosis
Chair: TBD
1:30 - 2:00
On Tests to Detect Interconnect Opens in Digital CMOS Circuits
S. Reddy, I. Pomeranz, C. Liu, and J. Howard
2:00 - 2:30
Test Generation for Interconnect Opens
X. Lin, J. Rajski (Mentor Graphics)
2:30 - 3:00
Using Design Validation Input Sequences to Determine Fault Criticality for Test Set Optimization
Y. Shi, K. DiPalma, W.-C. Hu, J. Dworak (Brown)
3:00 - 3:30
Diagnosis of Design Related Issues with Feature Encoding and Ranking
P. Bastani, N. Callegari, L. Wang (UCSB)
   
3:30 - 4:00 PM COFFEE BREAK
   
4:00 - 6:00 PM Test Using Wireless Communication
Chair: TBD
4:00 - 4:30
Wireless Testing of RAM Chips by HOY: Methodology, Architecture, and Prototype Implementation
T.-Y. Chang, C.-T. Huang, J.-J. Liou, C.-W. Wu, H.-P. Ma, C.-C. Tien, C.-H. Wang, C.-U. Yang
4:30 - 5:00
Wireless Communications Interface Design for HOY Wireless Testing Scheme
M.-Y. Chu, T.-Y. Chang, H.-J. Hsu, C.-Y. Lee, C.-F. Li, H.-P. Ma, C.-T. Huang, P.-C. Huang
5:00 - 5:30
Improving the Efficiency of Scan Test on Wireless HOY Test Platform
C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, C.-W. Wu
5:30 - 6:00
Automatic Wrapper Synthesis and Test Program Generation for Packet-based ATE Platforms
Y.-Y. Chen, C.-U. Yang, S.-Y. Chen, J.-J. Liou
   
DINNER (On Your Own)
   
April 8, 2008 (Tuesday)
   
7:30 - 8:30 AM CONTINENTAL BREAKFAST
   
8:30 - 10:30 AM Scan and BIST
Chair: TBD
8:30 - 9:00
Scan-Chain Design and Optimization for Three-Dimensional Integrated Circuits
X. Wu, P. Falkenstern, K. Chakrabarty, and Y. Xie
9:00 - 9:30
Using an X-Canceling MISR with Deterministic Observation for Increasing Output Compaction in Presence of Unknowns
R. Putman, R. Garg, and N.A. Touba (UT-Austin)
9:30 - 10:00
LBIST: a Myth or a Reality
S. Hwang, A. Guettaf, S. Ganta (Broadcom)
   
10:00 - 10:30 AM COFFEE BREAK
   
10:30-12:00PM Delay Test
Chair: TBD
10:30 - 11:00
Scalable Identification of High Quality Path Delay Tests Under Launch-Off-Capture Scan Architecture
E. Flanigan, M. Goparaju, D. Jayaraman, S. Tragoudas, M. Laisne, H. Cui, T. Petrov
11:00 11:30
An Efficient Dynamic Compaction Approach for Path Delay Test
Z. Wang, D.M.H. Walker (Texas A&M)
11:30 12:00
A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Structural Tests
J. Wang, J. Zeng, M. Mateja (AMD)
   
12:00 - 1:30 PM LUNCH
   
1:30 - 3:30 PM Fault Detection
Chair: Nur Touba, UT Austin
1:30 - 2:00
On Detecting Scan Chain Internal Faults
F. Yang, S. Chakravarty, N. Devta-Prasanna, S.M. Reddy, I. Pomeranz
2:00 - 2:30

A Methodology for Functional Black-Box Testing of Non-Processor Cores in an SOC
S. Gurumurthy, S. Sambamurthy, J. Abraham (UT-Austin)

2:30 - 3:00
Time-Multiplexed Online Checking: A Feasibility Study
M. Gao, H.-M. Chang, P. Lisherness, K.-T. Cheng
3:00 - 3:30
A Fault-Tolerant Mechanism for Analog Systems
A. Namazi, S. Askari, M. Nourani (UT-Dallas)
   
3:30 - 4:00 PM COFFEE BREAK
   
4:00 - 6:00 PM PANEL: Fast Clocks, Low Power, and Small Geometries: Big Problems for Test?
Moderator: TBD
 

Panelists:

TBA

 
6:30 - 9:30 PM SOCIAL EVENT AND DINNER
   
April 9, 2008 (Wednesday)
   
7:30 - 8:30 AM CONTINENTAL BREAKFAST
   
8:30 - 10:00 AM Debug and Scan
Chair: TBD
8:30 - 9:00
Expanding Observation Window for Trace Buffer via Selective Data Capture
J.-S. Yang, N. Touba (UT-Austin)
9:00 - 9:30
Study on Test Power Reduction for Scan-Based Hybrid BIST
M. Arai, A. Suto, K. Iwasaki
9:30 - 10:00
A Modified Scan-D Flip-Flop Design to Reduce Test Power
S. Khatri, S. Ganesan (Texas A&M)
   
10:00 - 10:30 AM COFFEE BREAK
   
10:30 - 12:00 PM Test Generation and Reliability
Chair: TBD
10:30 - 11:00
Test Generation for Designs with Multiple Clocks
X. Lin, S. Reddy (U. Iowa)
11:00 - 11:30
Reliable Nanometer VLSI Systems using NMR Logic Gates
A. Namazi, M. Nourani (UT-Dallas)
11:30 - 12:00
Design of a Fault Tolerant Carry Lookahead Adder
C.-Y. Huang, T.-H. Ko, J.-L. Huang
   
12:00 NOON ADJOURN
   
Committees
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General Chair
N. Mukherjee – Mentor G.

Past General Chair
S. Patil – Intel

Vice Chair
J. Dworak – Brown U.

Program Co-Chairs
N. Touba – U. Texas, Austin
S. Chakravarty - LSI

Panels Chair
V. Chickermane – Cadence

Publicity Chair
A. Jas – Intel

Finance Chair
C. Barnhart – Silicon Aid

Local Arrangements Chair
L. C. Wang – UC SB

European Liaison
M. Zwolinski – U. Southampton

Asian Liaison
C. W. Wu – Nat. Tsing Hua U.

Program Committee
M. Abadir – FreeScale
R. Aitken – ARM
K. Balakrishnan – AMD
S. Blanton – CMU
D. Burek – Magma
K. Chakrabarty – Duke U.
K.-T.Cheng – UC SB
A. Crouch – Inovys
R. Datta – TI
S. Davidson – Sun Micro.
C. Dixit – LSI
D. Goswami – Synopsys
A. Guettaf – Broadcom
M. Hsiao – Virginia Tech.
K. Iwasaki – Tokyo Metro. U.
R. Kapur – Synopsys
M. Laisne – QualComm
K.-J. Lee – Nat. Cheng-Kung U.
A. Majumdar – Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U. Texas
M. Nourani –U. Texas, Dallas
A. Orailoglu – UC San Diego
B. Pouya – Freescale
J.  Qian – Cisco
J. Rajski – Mentor Graphics
S. M. Reddy – U. Iowa
M. Tahoori – Northeastern U.
S. Tragoudas – S. Illinois U.
H. Walker – Texas A&M U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 15th International Test Synthesis Workshop (ITSW 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent - USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatle-lucent.com

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent - USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatle-lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Jill E. SIBERT
Raspberry Comm.
- USA
Tel. +1-484-894-1111
E-mail jill_sibert@raspberrycom.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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