TTTC's Electronic Broadcasting Service
Workshop on System Effects of Logic Soft Errors (SELSE 2008)
Advance Registration Deadline : March 14, 2008!
CALL FOR PARTICIPATION
The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concerns about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). Papers cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes.
Key topics include:
|For more information on registration please visit the online registration.|
Local Arrangements Chair
For more information, visit us on the web at: http://www.selse.org
The 4th IEEE International Workshop on Silicon Errors in Logic - System Effects (SELSE 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)
IEEE Computer Society- Test Technology Technical Council
TTTC 2ND VICE CHAIR
DESIGN & TEST MAGAZINE
& SOUTH PACIFIC
1ST VICE CHAIR
EAST & AFRICA
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