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International Test Synthesis Workshop (ITSW 2008)
University of California
CALL FOR PAPERS
Theme: At-Speed Scan: Challenges and Opportunities
Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.This year’s workshop will focus on at-speed scan tests, looking at various issues like hardware support, yield loss, test power, defect coverage, pseudo-functional tests and explore whether it is possible to replace functional delay tests with at-speed scan and still maintain product quality. As always, ITSW is open to all submissions in the area of test, including, but not limited, to the following:
For more information, please refer to the web site: http://www.tttc-itsw.org.
|To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format by January 9, 2008. Acceptance notifications will be sent out on February 27, 2008. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.
For general information, contact:
Submit extended abstracts via email to:
Past General Chair
Local Arrangements Chair
For more information, visit us on the web at: http://www.tttc-itsw.org
The 15th International Test Synthesis Workshop (ITSW 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).
IEEE Computer Society- Test Technology Technical Council
TTTC 2ND VICE CHAIR
DESIGN & TEST MAGAZINE
& SOUTH PACIFIC
1ST VICE CHAIR
EAST & AFRICA
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